一种可重构体系结构的声码器ALU设计

文章介绍了采用可重构体系结构的TR600语音编解码器中的ALU设计。重点讨论了ALU的资源部件、数据通路、指令及在设计中的平衡规则。该ALU采用VHDL语言描述,经过仿真、综合和FPGA验证后,完全符合设计要求。     

基于多项式符号代数方法的高层次数据通路的等价验证

基于BDD或布尔SAT的等价验证方法虽然能够成功验证低层次门级电路,但却难以满足高层次设计验证要求.由此,以多项式符号代数为理论基础,提出了一个高层次数据通路的等价验证算法.深入研究了使用多项式表达式描述复杂数据通路行为的方法,得到了高层次数据通路的多项式集合表示的一般形式.从多项式集合公共零点的角度定义了高层次数据通路的功能等价,给出了一个基于Gr(o)bner基计算的有效代数求解算法.针对不同基准数据通路的实验结果表明了该算法的有效性.     

基于FPGA CPU数据通路的设计与实现

针对MIPS CPU流水线工作过程产生的数据相关,基于FPGA设计并实现了能有效解决数据相关的数据通路.设计五种基本数据通路,并采用流水线技术将它们整合成五级数据通路;在EX段后到ALU之间和WB段后到ALU之间构建旁路通路,从而形成总的数据通路;使用VHDL实现数据通路;编写测试程序对数据通路进行验证,并在FPGA平台上进行仿真验证.结果表明:所设计的数据通路能使数据正常流动,解决由数据相关产生的断流问题.     

一种支持SIMD指令的低功耗分裂式ALU设计

在面向多媒体运算的高性能、低功耗DSP芯片MD32设计中，支持SIMD指令的分裂式、低功耗ALU设计是实现其没计目标的重要环节。该文提出了利用基于资源共享的设计思想，以超前进位加法器(Catry Look-ahead Adder)为核心构造数据处理单元，完成算术以及逻辑运算，减少了ALU模块的面积，同时均衡了不同数据通路长度，并且采用先进行数据选择，而后进行数据处理的设计原则，降低不使用模块的活动度，减少了功耗。根据Design Power分析其综合后门级实现结果，芯片面积可减少8％，功耗可减少51％。     

基于加权数据通路的RTL级低功耗SoC设计

低功耗是SoC设计与评估的重要技术指标之一,现利用加权数据通路,提出一种新的低功耗SoC设计方法。该算法首先利用程序切片技术提取RTL级数据通路,然后采用贝叶斯网络训练获得各数据通路的权重(使用频率),以形成加权数据通路,最后根据各路径权值控制门控信号的产生,对权值小的通路优先插入门控逻辑或合并门控逻辑,从而有效降低系统功耗。实验结果表明,该算法与已有ODC低功耗算法相比功耗平均下降8. 38%,面积开销平均减少6.8%,同时数据通路的简化也使得算法计算负荷大幅下降。     

基于NHibernate的数据持久化方案

分析目前广泛使用的对象关系映射（ORM）组件——NHibernate,针对NHibernate的不足提出改进的ORM模型,根据该模型设计并实现基于.NET平台的轻量级ORM组件——MYPL,利用该组件无须编写任何映射文件即可实现对象关系映射等数据持久化操作,并能降低业务层和数据层之间的耦合,提高系统的扩展性、可维护性和应用系统的开发效率。     

VHDL高级综合系统中多层次、多目标工艺映射策略及其实现

从国内实际出发,在分析当前工艺映射技术的基础上,提出从高层次（ＲＴＬ）和逻辑级两个层次上进行工艺映射的策略。提出并讨论了基于知识的高层次（ＲＴＬ）工艺映射方法,并将该方法与传统的逻辑级工艺映射方法相结合,建造ＭＬＴＭＭＴ（Ｍｕｌｅｔ－Ｌｅｖｅｌ Ｔｅｃｈｎｏｌｏｇｙ Ｍａｐｐｉｎｇ ｆｏｒ Ｍｕｌｔｉ－Ｔａｒｇｅｔ,多层次、多目标工艺映射）系统。在ＭＬＴＭＭＴ的具体实现上,采用了基于知识与基于算法     

改进量子算法的片上网络映射研究

片上网络（NoC）是解决片上系统（SoC）之间各个IP核通信的主要方法。其中NoC的映射是整个NoC设计过程中最为关键的步骤之一。采用一种改进的方法解决NoC映射问题,该方法基于量子进化算法,并在算法中采用一种改进的更新方法,之后引入精英策略,让所有中间过程的解都参与到迭代中,选择其中最好的解作为每次迭代的NoC映射最终解。使用该方法建立在延时约束下的NoC映射功耗数学模型,实验表明,该方法在NoC映射中能达到降低通信功耗的目的。     

面向高层次综合的自定义指令自动识别方法

针对在高层次综合（HLS）过程中性能提升、功耗降低困难等问题,提出了一种面向高层次综合的自定义指令自动识别方法。在高层次综合过程之前实现对自定义指令的枚举和选择,从而为高层次综合提供通用的自定义指令识别方法。首先,将高层次源代码转换为控制数据流图（CDFG）,实现了对源代码的预处理;其次,基于控制数据流图内的数据流图（DFG）,采用子图枚举算法以自底而上的方式枚举出所有连通凸子图,有效提高了用户可灵活修改约束条件的能力;然后,分别从面积、性能和代码量三个角度考虑,利用子图选择算法选择部分最佳子图作为最终的自定义指令;最后,用所选的自定义指令重新生成新代码作为高层次综合工具的输入。与传统高层次综合相比,采用基于出现频率的模式选择可平均减少19.1%的面积,采用基于关键路径的子图选择可平均减少22.3%的时延。此外,与TD算法相比,所提算法的枚举效率平均提升70.8%。实验结果表明,自定义指令自动识别方法使高层次综合在电路设计中能够显著地提升性能,减少面积和代码量。     

Authorization Translation for XML Document Transformation

XML access control models proposed in the literature enforce access restrictions directly on the structure and content of an XML document. Therefore access authorization rules (authorizations, for short), which specify access rights of users on information within an XML document, must be revised if they do not match with changed structure of the XML document. In this paper, we present two authorization translation problems. The first is a problem of translating instance-level authorizations for an XML document. The second is a problem of translating schema-level authorizations for a collection of XML documents conforming to a DTD. For the first problem, we propose an algorithm that translates instance-level authorizations of a source XML document into those for a transformed XML document by using instance-tree mapping from the transformed document instance to the source document instance. For the second problem, we propose an algorithm that translates value-independent schema-level authorizations of non-recursive source DTD into those for a non-recursive target DTD by using schema-tree mapping from the target DTD to the source DTD. The goal of authorization translation is to preserve authorization equivalence at instance node level of the source document. The XML access control models use path expressions of XPath to locate data in XML documents. We define property of the path expressions (called node-reducible path expressions) that we can transform schema-level authorizations of value-independent type by schema-tree mapping. To compute authorizations on instances of schema elements of the target DTD, we need to identify the schema elements whose instances are located by a node-reducible path expression of a value-independent schema-level authorization. We give an algorithm that carries out path fragment containment test to identify the schema elements whose instances are located by a node-reducible path expression.     

声码器中一种四级可重构ALU的研究与设计

在面向语音编解码算法实现的高性能声码器设计中,支持可变长VLIW指令集的ALU单元是实现其设计目标的重要环节.本文提出一种四级可重构的ALU设计,以前缀算法加法器为核心,并通过操作数和资源的重构,能在单周期内完成81种复合算术逻辑运算,同时将其控制编码压缩了58.93%以适应指令集的宽度约束,高效实现了算法中潜在的高并行性,很好的满足了运算密集型的算法应用需求.     

Database reverse engineering: From the relational to the binary relationship model

This paper describes an algorithmic method for transforming a relational database schema to a binary-relationship one. The source schema may consist of relations that are at any level of normalization, and the designer may add semantic information on the source schema, such as the definition of candidate keys, foreign keys, functional dependencies of various types, multi-valued dependencies, many-to-many constraints, inclusion dependencies, and others. Based on this information, the multi-stage transformation algorithm applies mapping rules to generate object-types, binary-relationships and constraints in the target conceptual schema. The method is implemented as a PC-based tool, utilizing Ingres, SQL and C, and is part of a comprehensive database design tool for both forward and reverse engineering.     

A cost-efficient and versatile sanitizing algorithm by using a greedy approach

In a very large database, there exists sensitive information that must be protected against unauthorized accesses. The confidentiality protection of the information has been a long-term goal pursued by the database security research community and the government statistical agencies. In this paper, we proposed greedy methods for hiding sensitive rules. The experimental results showed the effectiveness of our approaches in terms of undesired side effects avoided in the rule hiding process. The results also revealed that in most cases, all the sensitive rules are hidden without generating spurious rules. First, the good scalability of our approach in terms of database sizes was achieved by using an efficient data structure, FCET, to store only maximal frequent itemsets instead of storing all frequent itemsets. Furthermore, we also proposed a new framework for enforcing the privacy in mining association rules. In the framework, we combined the techniques of efficiently hiding sensitive rules with the transaction retrieval engine based on the FCET index tree. For hiding sensitive rules, the proposed greedy approach includes a greedy approximation algorithm and a greedy exhausted algorithm to sanitize the database. In particular, we presented four strategies in the sanitizing procedure and four strategies in the exposed procedure, respectively, for hiding a group of association rules characterized as sensitive or artificial rules. In addition, the exposed procedure would expose missing rules during the processing so that the number of missing rules could be lowered as much as possible.     

基于区域的图像融合方法

针对传统像素级图像融合方法割裂像素间联系的问题,提出了一种基于区域的图像融合方法.首先对源图像进行离散小波框架分解,对其中一幅的低频子图利用模糊c均值聚类方法进行区域分割,并将区域表示线性映射到其他源图像.然后利用区域小波系数的结构相似度和区域能量构造融合规则,依据融合后的系数重构可得到融合图像.实验结果表明该方法能够有效地融合源图像信息并保持源图像特征.     

视频传感器网络中基于移动目标轨迹预测的K级覆盖增强算法

从视频传感器节点的有向感知模型出发,深入研究了移动目标K级覆盖问题。首先扩展了可旋转的视频传感器节点有向感知模型,分析了监控区域内移动目标可能的行为,定义了最小旋转角度的移动目标K级覆盖问题并给出了对应的数学描述。然后设计了一种目标轨迹点预测方法,提出了基于预测的分布式贪心K级覆盖算法。最后引入了优化的覆盖质量评价指标,通过一系列仿真实验验证了算法的有效性。     

电路原理图中两边网格通道布线的类贪婪算法

贪婪算法是VLSI设计中通道布线的常用算法，在电路原理图的自动布图中，也会遇到通道布线的问题。但传统的贪婪算法着重于使通道面积最小化，不能满足原理图中对布线结果有序化的要求。提出类贪婪算法，在原贪婪算法的基础上，通过修改处理规则，使得布线结果更加整齐有序，便于阅读，同时也保留了原算法简洁的优点。     

基于用户自描述标签的层次分类体系构建方法

模式层知识对于语义万维网的发展非常重要,然而当前开放链接数据(LOD)中模式层知识的数量十分有限,为突破这一局限,提出一种基于社交网络中用户自描述标签的层次分类体系构建方法。该方法首先设计基于搜索引擎的标签分块算法,将描述相同话题的标签划分到同一标签块中,然后采用基于半监督学习的标签传播算法挖掘相同标签块中标签间的上下位关系,最后运用基于启发式规则的贪心算法来构建层次分类体系,从而在社交站点中构建出大规模且高质量的层次分类体系。实验结果表明,该构建方法与现有相关工作相比在准确率、召回率以及F值上均有明显提高。     

Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures

Emerging nano-devices with the corresponding nano-architectures are expected to supplement or even replace conventional lithography-based CMOS integrated circuits, while, they are also facing the serious challenge of high defect rates. In this paper, a new weighted coverage is defined as one of the most important evaluation criteria of various defect- tolerance logic mapping algorithms for nanoelectronic crossbar architectures functional design. This new criterion is proved by experiments that it can calculate the number of crossbar modules required by the given logic function more accurately than the previous one presented by Yellambalase et al. Based on the new criterion, a new effective mapping algorithm based on genetic algorithm (GA) is proposed. Compared with the state-of-the-art greedy mapping algorithm, the proposed algorithm shows pretty good effectiveness and robustness in experiments on testing problems of various scales and defect rates, and superior performances are observed on problems of large scales and high defect rates.