Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UML-based hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS cannot only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.     

SoC设计中一种软硬件划分的性能评价方法

介绍了一种在SoC系统级设计中对软硬件划分进行评价的方法。系统层设计中，对设计方案的性能、成本和功耗的准确估计，是取得高质量设计的必要条件。讨论了基于平台的设计中，利用基于事务级仿真的方法对系统的软硬件划分结果进行评价的方法。     

A Modularized Personal Robot DRP I: Design and Implementation

In this paper, we investigate comprehensive issues of modularized robot systems and present architecture for effective development of personal robots. The proposed architecture includes the interface and interaction methodology of the hardware modules and the software among the modules. Based on the architecture, we present a fully modularized personal robot dynamically reconfigurable personal robot I. Its hardware modules are easily added to or removed from the original system, and also the distributed software functions of the modules are rearrangeable accordingly. We focus on how to effectively build up the robot, and discuss the dynamically reconfigurable features of it for evaluating the proposed idea and approach.     

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD tools and platforms incapable of efficiently exploring the design space. As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS). Computation-intensive network security functions, implemented as reconfigurable hardware functions, can be configured on-demand into a DPRNSS at run-time. Thus, UCoP not only supports dynamic adaptation to different environment conditions, but also increases hardware resource utilization. UCoP supports design space exploration for reconfigurable systems in three folds. Firstly, it provides reusable models of typical reconfigurable systems that can be customized according to user applications. Secondly, UCoP provides a partially reconfigurable hardware task template, using which users can focus on their hardware designs without going through the full partial reconfiguration flow. Thirdly, UCoP provides direct interactions between UML system models and real reconfigurable hardware modules, thus allowing accurate time measurements. Compared to the existing lower-bound and synthesis-based estimation methods, the accurate time measurements using UCoP at a high abstraction level can more efficiently reduce the system development efforts.     

Agent-based reconfigurable architecture for real-time object tracking

Most conventional object tracking algorithms are implemented on general-purpose processors in software due to its great flexibility. However, the real-time performance is hard to achieve due to the inherent characteristics of the sequential processing of these processors. To tackle this issue, a reconfigurable system-on-chip (rSoC) platform with microprocessors and FPGAs is applied in this paper. To simplify the hardware/software interface, a Belief–Desire–Intention (BDI)-based multi-agent architecture is proposed as the unified framework. Then an agent-based task graph and two heuristic partitioning methods are proposed to partition the hardware and software on an rSoC platform. Compared to the module-based architecture, this BDI-based multi-agent architecture provides more efficiency, flexibility, autonomy, and scalability for the real-time tracking systems. A particle swarm optimization (PSO)-based object detection and tracking algorithm is applied to evaluate the proposed architecture. Extensive experimental results of object tracking demonstrate that the proposed architecture is efficient and highly robust with real-time performance.     

Protocol wrappers for layered network packet processing inreconfigurable hardware

A library of layered protocol wrappers processes Internet packets in reconfigurable hardware. Collectively, the wrappers simplify and streamline the implementation of high-level networking functions by abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform called the field-programmable port extender (FPX). The library processes asynchronous transfer mode (ATM) cells, ATM adaptation layer 5 (AAL5) frames, Internet protocol (IP) messages, and user datagrarn protocol (UDP) packets directly in hardware. Applications can process data at several layers of the protocol stack using the library of wrappers discussed in this article. Layers are important for networks because they let applications abstract from above and below details of the network protocols. At the lowest layer, networks modify raw data passing between interfaces. At higher levels, the applications process variable length frames or IP packets.A network platform called the field-programmable port extender (FPX) streamlines and simplifies network transmission processing directly in hardware     

Real-time hardware–software embedded vision system for ITS smart camera implemented in Zynq SoC

The article demonstrates the usefulness of heterogeneous System on Chip (SoC) devices in smart cameras used in intelligent transportation systems (ITS). In a compact, energy efficient system the following exemplary algorithms were implemented: vehicle queue length estimation, vehicle detection, vehicle counting and speed estimation (using multiple virtual detection lines), as well as vehicle type (local binary features and SVM classifier) and colour (k-means classifier and YCbCr colourspace analysis) recognition. The solution exploits the hardware–software architecture, i.e. the combination of reconfigurable resources and the efficient ARM processor. Most of the modules were implemented in hardware, using Verilog HDL, taking full advantage of the possible parallelization and pipeline, which allowed to obtain real-time image processing. The ARM processor is responsible for executing some parts of the algorithm, i.e. high-level image processing and analysis, as well as for communication with the external systems (e.g. traffic lights controllers). The demonstrated results indicate that modern SoC systems are a very interesting platform for advanced ITS systems and other advanced embedded image processing, analysis and recognition applications.     

基于嵌入式Web服务器的网络设备测控系统设计

面向Internet是设备网络化设计的发展方向。介绍了互联网在嵌入式设备中的应用，说明了基于嵌入式Web服务器的网络智能设备测控系统的设计方案和软、硬件的实现。硬件上选用Rabbit 2000网络微处理器作为网络接口的Web服务器，构建嵌入式SoC Web服务器，底层软件采用Dynamic C软件开发环境。详细阐述了构建嵌入式Web服务器的具体技术及相关的实现方案，以及实现用TCP、UDP报文进行网络通信、串行口数据通信和对网络智能设备的测控技术等，并给出相关系统软件的程序代码及流程图。目前该系统的运行效果良好。     

A binary partitioning approach to image compression using weighted finite automata for large images

Fractal-based image compression techniques give efficient decoding time with primitive hardware requirements, and favor real-time communication purposes. One such technique, the weighted finite automata (WFA), is studied on grayscale images. An improved image partitioning technique—the binary or bintree partitioning—is tested on the WFA encoding method. Experimental results show that binary partitioning consistently gives higher compression ratios than the conventional quadtree partitioning method for large images. Moreover, the ability to decode images progressively rendering finer and finer details can be used to display the image over a congested and loss-prone network such as the image transport protocol (ITP) for the Internet, as well as to pave way for multilayered error protection over an often unreliable networking environment. Also, the proposed partitioning approach can be parallelized to reduce its high encoding complexity.     

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing

Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.

基于HKS1553BCRT芯片的1553B总线通信软件设计

为了提高1553B总线通信模块的统一性简化设计难度,文中选用HKS1553BCRT芯片作为系统开发的硬件平台。该硬件平台由于采用内部集成1553B协议处理器的高性能SoC,可以很好的解决多路1553B总线接口模块版本众多、互不兼容、硬件系统设计复杂的问题。基于该平台设计了一款通用的1553B通信软件,可同时支持静态总线和动态总线两种不同的工作模式,提出并实现了改进型静态总线控制（ImprovedStaticBusControllerISBC）协议。进一步满足了不同系统下数据传输需求,改善了1553B总线对实时消息的响应速度,本软件数据结构简洁、算法合理,对同类软件设计有一定的借鉴意义。     

A Hopfield neural network approach for power optimization of real-time operating systems

The RTOS (Real-Time Operating System) is a critical component in the SoC (System-on-a-Chip), which is the main body for consuming total system energy. Power optimization based on hardware–software partitioning of a RTOS (RTOS–Power partitioning) can significantly minimize the energy consumption of a SoC. This paper presents a new model for RTOS–Power partitioning, which helps in understanding the essence of the RTOS–Power partitioning techniques. A discrete Hopfield neural network approach for implementing the RTOS–Power partitioning is proposed, where a novel energy function, operating equation and coefficients of the neural network are redefined. Simulations are carried out with comparison to other optimization techniques. Experimental results demonstrate that the proposed method can achieve higher energy savings up to 60% at relatively low costs of less than 4k PLBs while increasing the performance compared to the purely software realized SoC–RTOS.     

Message-Based Evaluation in Scheme for High-Level Robot Control

In this paper, we present a method for high-level control of robots whose low-level software is based on dynamically reconfigurable, reusable real-time software modules. Our approach is to use an embedded interpreter for a general-purpose programming language to direct the operation of the low-level modules toward meeting the task-level goals of the robot. To this end, we present RSK, a virtual-machine kernel implementing a Scheme interpreter capable of hard real-time operation, and employing a method of code execution we call message-based evaluation (MBE) . MBE is a novel combination of a traditional code execution model and a message-passing architecture, which simplifies the process of writing code for managing the robot's reconfigurable subsystem.     

A dynamically reconfigurable multiprocessor system for high-order bidirectional associative memory-based image recognition

A High-Order Bidirectional Associative Memory (HOBAM) based image recognition system and a dynamically reconfigurable multiprocessor system that achieves real-time response have been utilized to recognize corrupt images of human faces (faces obscured by hats, glasses, masks or slight translation and scaling effects). In addition, the HOBAM, in conjunction with edge detection techniques, has been used to recognize isolated objects within multiple-object images. Successful recognition rates have been achieved in both cases.A dynamically reconfigurable multiprocessor system and parallel software have been developed to achieve real-time response for image recognition. The system consists of Inmos transputers and cross-bar switches (IMS C004) with communication links dynamically connected by circuit switching. The use of transputers and cross-bar switches combined to form a low-cost multiprocessor system connected by a switching network is reported. Moreover, the switching network, which makes message routing unnecessary, simplifies the design of the communication in parallel software. Although the HOBAM is a fully connected network, the algorithm minimizes the amount of information that needs to be exchanged between processors using a data compression technique. The detailed design of both hardware and software are discussed, as well as the use of parallel processing to significantly increase the speed ratio. The architecture of the experimental system is a cost-effective design for an embedded system for neural network applications on computer vision.     

一种基于离散Hopfield神经网络的RTOS功耗优化方法

RTOS(Real-Time Operating System,实时操作系统)是SoC(System-on-a-Chip,系统芯片或片上系统)的一个重要组成部分,其功耗一般约占整个系统功耗30～40%的比例,而基于软/硬件划分的RTOS功耗优化方法(简称RTOS-Power划分)能够明显地减少SoC的功耗.因此,文中首先引入了RTOS-Power划分问题的一个新模型,这有助于理解RTOS-Power划分的本质.然后,提出了一种基于离散Hopfield神经网络的RTOS-Power划分方法,重新定义了神经网络的神经元表示、能量函数、运行方程和系数.最后,对该方法进行了仿真实验,并同遗传算法和蚂蚁算法进行了性能比较.实验结果表明:该文提出的方法能够以相对较小的代价(FPGA开销小于4K个可编程逻辑块)取得高达60%的功耗节省,同时,与纯软件实现的RTOS相比,系统性能也得到了相应的提高.     

面向应用的可重构编译器ASCRA(英文)

在很多应用领域已经开展了可重构计算的研究,但是由于缺乏高层设计工具,设计者需要较深的软件和硬件专业知识才能开发GPP/RAU架构的程序,阻碍了其大规模应用。提出了一种面向应用的可重构编译器——ASCRA的初始架构,它可以自动将C语言映射为VHDL语言,从而解决可重构计算中自动编译工具的瓶颈。ASCRA编译器主要研究软硬件划分技术和面向硬件的优化技术,如脉动阵列、循环流水技术。在ML505开发平台上,设计实现了ASCRA编译器的验证平台,并通过实验给出了核心程序段生成VHDL代码的综合信息。     

面向可重构控制器实时中间件的设计与实现

可重构控制器的出现要求系统软件模块不但要满足性能和精度要求,还应具有模块化、可集成、可重用等特性.如果将实时中间件引入到控制器的设计中,由中间件管理模块间的交互,可实现控制器的可重构.建立基于RTLinux和实时CORBA的实时中间件平台,需要将CORBA引入RTLinux实时内核空间.该文给出了RTLinux实时内核中的实时CORBA和minimum CORBA实现RTCK的设计,并基于RTLinux MBuff共享内存驱动和实时FIFO设计和实现了GIOP通信协议,最后给出了RTCK与TAO的延迟抖动测试结果并做了相关的分析.     

基于FPGA的SoC/IP验证平台的设计与应用

采用Altera公司CycloneII系列的FPGA设计了一个基于片上总线的SoC原型验证平台,并将VxWorks嵌入式操作系统应用于此平台,通过软硬件协同验证方法,验证了平台的可靠性。该平台在CF卡及通用智能卡SoC芯片验证中得以应用。     

基于AMBA总线的SoC平台的设计和验证

SoC是大规模集成电路发展的必然趋势。完整的SoC平台包括硬件平台和软件平台,硬件平台上运行软件,软件平台又可以进一步验证硬件平台。本文设计了一个基于AMBA总线的SoC硬件平台,并以μClinux操作系统为基础构造软件平台。通过软硬件协同验证的方法,验证了平台的可靠性。该平台已在HDTVSoC设计中得到应用。     

Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm

In this paper a pipelined architecture of a high speed network security processor (NSP) for SSL/TLS protocol is implemented on a system on chip (SoC) where hardware information of all encryption, hashing and key exchange algorithms are stored in Secure Digital (SD) card in terms of bit files, in contrary to recent ones where all are actually implemented in hardware. The SoC works as NSP for the system (PC), which is running the application. Through the SoC the security algorithms are implemented and it also provides the Ethernet communication interface. The NSP finds applications in e-commerce, virtual private network (VPN) and in other fields that require data confidentiality.The motivation of the present work is to dynamically execute applications in embedded systems having strict resource and power budgets maintaining a stipulated throughput. An appropriate cipher suite is chosen following a proposed preferential algorithm based on Efficient System Index (ESI) budget comprising of throughput, power and resource given by the user. The bit files of the chosen security algorithms are downloaded from the SD card to the partial region of Field Programmable Gate Array (FPGA). The proposed SoC controls data communication between an application running in a system through a PCI and an Ethernet interface of a network. The proposed design uses partial reconfiguration feature of ISE14.4 suite with ZYNQ 7z020-clg484 FPGA platform. The performances of the implemented crypto algorithms are considerably better in terms of power throughput and resource than the existing works reported in literatures.