A Second-Order All-Digital Phase-Locked Loop

A simple second-order digital phase-locked loop has been designed to synchronize itself to a square-wave subcarrier. Analysis and experimental performance are given for both acquisition behavior and steady-state phase error performance. In addition, the damping factor and the noise bandwidth are derived analytically. Although all the data are given for the square-wave subcarrier case, the results are applicable to arbitrary subcarriers that are odd symmetric about their transition region.     

一种基于线性增强TDC的ADPLL设计

锁相环作为片内高速时钟的提供者,在现代电路中至关重要。提出了一种全数字锁相环的设计方案,输出频率为250 MHz,锁定时间为2 μs,峰峰抖动为76 ps,与传统锁相环相比,具有面积小、功耗低、可移植性好、抗干扰能力强等优点。时间数字转换器(TDC)是全数字锁相环的重要组成部分,采用线性增强算法后,与现有TDC相比,具有动态范围大、分辨率高等特点,且大大减小了积分非线性。     

辐照加固的500MHz锁相环设计

设计了一款与CSMC 0.5μm CMOS工艺兼容的频率为500 MHz的辐照加固整数型锁相环电路,研究了总剂量辐照以及单粒子事件对锁相环电路主要模块及整个系统性能的影响。此外,通过修正BSIM3V3模型的参数以及施加脉冲电流源来模拟总剂量辐照效应和单粒子事件,对锁相环整体电路进行了电路模拟仿真以及版图寄生参数提取后仿真。模拟结果表明,辐照总剂量为1Mrad(Si)时锁相环电路仍能正常工作,产生270.58~451.64 MHz的时钟输出,峰峰值抖动小于100 ps,锁定时间小于4μs;同时在对单粒子事件敏感的数字电路的主要节点处施加脉冲电流源后,锁相环电路均能在短时间内产生稳定的输出。     

一种500MHz高性能锁相环的设计

随着专用集成芯片（ASIC）和系统芯片（SOC）的飞速发展,芯片内部生成可变频率的稳定时钟变得至关重要,设计一个高性能锁相环正是适应了这样的需求。本文在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构。它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片（ASIC）和系统芯片（SOC）的实现提供最基础且最重要的可应用时钟产生电路。模拟结果表明：该锁相环可稳定输出500 MHz时钟信号,稳定时间小于700ns,在1．8V电源下的功耗小于18mW,噪声小于180mV。     

一种500MHz高性能锁相环的设计

在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构.它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片(ASIC)和系统芯片(SOC)的实现提供最基础且最重要的可应用时钟产生电路.模拟结果表明,该锁相环可稳定输出500MHz时钟信号,稳定时间小于700 ns,在1.8V电源下的功耗小于18mW,噪声小于180mV.     

A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time

A time-constant calibrated phase-locked loop with a fast-locked time is presented. A variable capacitance multiplier (VCM) is developed to adjust the equivalent capacitance in the loop filter. And a calibration circuit is used to allow the time constant of the loop filter to track with the reference clock. By using the proposed time-constant calibration circuit and the VCM, the fast acquisition time is achieved and the loop capacitance is also multiplied. A prototype has been fabricated in a 0.35-mum CMOS process to demonstrate the proposed circuit     

A Beam-Steering and -Switching Antenna Array Using a Coupled Phase-Locked Loop Array

We present the analysis and experimental results of a beam-steering and -switching antenna array using coupled oscillators and phase-locked loops. With the use of a type-II coupled phase-locked loop array and an external reference signal, the antenna array can steer its beam by a single control voltage, reduce the beam-pointing error arising from the phase errors of the oscillator array, and hold its output frequency stably at the reference signal frequency in operation. Using a double-pole double-throw switch and a difference amplifier at the center element of the antenna array, one can switch the array radiation pattern between the sum pattern and the difference pattern. Moreover, the beam-scanning range is extended to plusmn 90deg by properly using frequency prescalers in the phase-locked loops. The radiation characteristics of a three-element antenna array are measured to verify the array performance.     

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively     

一种应用于HDMI接收端的宽频带锁相环设计

基于110 nm CMOS工艺设计了一种应用于HDMI接收端电路的宽频带低抖动锁相环。采用一种改进型双环结构电荷泵,在25～250 MHz的宽输入频率范围内实现了快速锁定。通过高相噪性能的伪差分环形振荡器产生了调谐范围为125 MHz～1.25 GHz的时钟信号。仿真实验结果表明,该锁相环的锁定时间小于1.2μs,在振荡器工作频率为0.8 GHz时,其相位噪声为-100.0 dBc/Hz@1 MHz,输出时钟峰峰值抖动为4.49 ps。     

A New Approach to Prosthetic Control: EEG Motor Signal Tracking With an Adaptively Designed Phase-Locked Loop

The feasibility of using brain waves to control an externally powered prosthetic device for amputees was investigated. Two subjects were studied; one normal and one with a right hand disarticulation. Each subject, otherwise at rest, performed the protocol of voluntarily, repetitively opening and closing his hand. The normal accomplished this, while the amputee attempted to use her missing limb as if it were present. The time between opening and the next closing, and between closing and the next opening, was approximately 2 s. Simultaneously with this procedure, electroencephglograms (EEGs) were recorded from scalp electrodes presumably overlying the motor cortex on the left side, and an electromyogram (EMG) was taken from right forearm surface electrodes. The EEG and EMG were recorded on a polygraph and on magnetic tape. The latter recording was later sampled at 128 samples/s and quantized to 210 levels.     

一种宽频带低抖动锁相环

详细分析了自偏置锁相环(PLL)的工作原理,采用一种新颖的折叠式电荷泵(CP)结构,包含一个宽摆幅电流镜,实现了更好的电流匹配,降低了PLL的系统抖动。该PLL采用130 nm CMOS工艺进行制造。VCO的调频范围为0.43~1.54 GHz。在1.25 GHz工作频率下,频偏1 MHz处,PLL的相位噪声为-89.6 dBc/Hz,均值抖动为3.03 ps,峰峰值抖动为18.16 ps,芯片面积仅为0.34 mm²。     

A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loop bandwidth is set to 400 kHz with a 25 MHz reference. The in-band phase noise contribution from the TDC is -116 dBc/Hz, the phase noise is -117 dBc/Hz at high band (1.8 GHz band) 400 kHz offset, and the RMS phase error is 0.3deg.     

一种低参考杂散高PSNR的I型锁相环

基于GF 130 nm CMOS工艺,设计了一种低参考杂散、高电源噪声抑制比(PSNR)的I型锁相环。相较于电荷泵型锁相环,I型锁相环存在锁定范围小、参考杂散性能差等缺点。此外,压控振荡器是对电源噪声敏感的模拟电路,电源线上的噪声会恶化振荡器的输出抖动性能。通过引入采样保持电路和电源电压整形器,降低了I型锁相环的参考杂散和电源噪声敏感系数。仿真结果表明,设计的I型锁相环的工作频率范围为2.1~2.8 GHz,参考杂散为－66 dBc,PSNR为－25 dB,功耗为10 mW,芯片占用面积为0.009 mm²。     

Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency- and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from ?10 to 60 °C and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.     

A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 $mu$ m CMOS

In this letter, a multi-gigahertz phase-locked loop (PLL) with a compact low-pass filter is presented. By using a novel dual-path control in the PLL architecture, the capacitance in the loop filter can be effectively reduced for high-level integration while maintaining the required loop bandwidth. Consequently, the noise resulted from off-chip components is therefore eliminated, leading to lower timing jitter at the PLL output waveforms. In addition, the timing jitter is further suppressed due to the use of decomposed phase and frequency detection. Based on the proposed techniques, a 10 GHz PLL is implemented in 0.18 mum CMOS for demonstration. Consuming a dc power of 113 mW from a 1.8 V supply, the fabricated circuit exhibits a locking range from 10.1 to 11 GHz. At an output frequency of 10.3 GHz, the measured peak-to-peak and rms jitter are 3.78 and 0.44 ps, respectively.     

500MHz～3.5GHz高性能宽带双极化天线的研制

本文研制了一种500MHz～3.5GHz高性能宽带双极化四脊喇叭天线.首先采用化四脊喇叭天线为双脊喇叭天线的设计方法设计初步模型,然后利用HFSS对四脊喇叭天线的参数及结构进一步优化,提高了两个极化端口的驻波比性能:一方面对四脊波导各个参数对驻波比的影响进行分析,选出最优的参数组合:另一方面,结构上采用渐变结构、脊末端顶入导体杆、特制细探针馈电等设计.最终的测量结果显示,优化后的天线具备高性能:工作频带宽、方向图好,驻波比低,且两个极化端口的驻波比一致性好.     

A CMOS transconductor with 80-dB SFDR up to 10 MHz

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80-dB spurious-free dynamic range (SFDR) for 3.6-V_pp differential inputs up to 10 MHz. The combination of resistors at the input and negative feedback around the operational transconductance amplifier (OTA) allows this transconductor to accommodate a differential input swing of 4 V with a 3.3-V supply. The total harmonic distortion (THD) of the transconductor is -77 dB at 10 MHz for a 3.6-V_pp differential input and third-order intermodulation spurs measure less than -79 dBe for 1.8-V_pp differential inputs at 1 MHz. The transconductance core dissipates 10.56 mW from a 3.3-V supply and occupies 0.4 mm² in a 0.35-μm CMOS process     

A 10:1 Unequal Wilkinson Power Divider Using Coupled Lines With Two Shorts

A novel unequal Wilkinson power divider is presented. A coupled-line section with two shorts is proposed to realize the high characteristic impedance line, which cannot be implemented by conventional microstrip fabrication technique due to fabrication limitation. The proposed coupled-line structure is compatible with single layer integration and can be easily designed based on an even-odd mode analysis. As a design example, a 10:1 Wilkinson power divider at 2 GHz is fabricated and measured. The measured $-10~{rm dB}$ bandwidth of $S_{11}$ is about 16%, and the isolation $S_{32}$ is better than $-20~{rm dB}$ . The measured amplitude balance between output port 2 and port 3 is between $-10.20~{rm dB}$ and $-9.52~{rm dB}$, and the corresponding phase difference is between 0$^{circ}$ and 4.6$^{circ}$.