A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

A 1-GHz BiCMOS RF front-end IC

An RF front-end IC containing a low-noise amplifier and mixer is described. On-chip temperature and supply-voltage compensation is used to stabilize circuit performance. Realized in a BiCMOS process, the circuit consumes 13.0-mA total current from a 5-V supply. The amplifier gain at 900 MHz is 16 dB, the noise figure is 2.2 dB, and the input third-order intermodulation intercept is -10 dBm. The mixer input third-order intermodulation intercept is +6 dBm with 15.8 dB noise figure     

Calibration techniques of active BiCMOS mixers

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-μm SiGe BiCMOS process and is characterized at 900 MHz     

An Si-SiGe BiCMOS direct-conversion mixer with second-order and third-order nonlinearity cancellation for WCDMA applications

This paper presents a general analysis of the third-order nonlinearity of a differential common-emitter RF amplifier and an improved technique to cancel the third-order nonlinearity. A thorough analysis of the mechanisms leading to the second-order nonlinearity of bipolar double-balanced active mixers is also presented. An SiGe BiCMOS WCDMA direct-conversion mixer is designed based on the third- and the second-order cancellation schemes. The mixer achieves +6-dBm third-order input intercept point, +49-dBm second-order input intercept point, 16-dB gain and 7.2-dB double-sideband noise figure with only 2.2-mA current at 2.1 GHz.     

RF front-end of direct conversion receiver RFIC for cdma-2000

We report on the front-end of a highly integrated dual-band direct-conversion receiver IC for cdma-2000 mobile handset applications. The RF front-end included a CELL-band low-noise amplifier (LNA), dual-band direct-conversion quadrature I/Q down-converters, and a local-oscillator (LO) signal generation circuit. At 2.7 V, the LNA had a noise figure of 1.2 dB and input third-order intermodulation product (IIP3) of 9 dBm. I/Q down-converters had a noise figure of 4-5 dB and IIP3 of 4-5 dBm and IIP2 of 55 dBm. An on-chip phase-locked loop and external voltage-controlled oscillator generated the LO signal. The receiver RFIC was implemented in a 0.35-/spl mu/m SiGe BiCMOS process and meets or exceeds all cdma-2000 requirements when tested individually or on a handset.     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A direct conversion receiver with an IP2 calibrator for CDMA/PCS/GPS/AMPS applications

A second-order intercept point (IP2) calibration technique is developed using common-mode feedback (CMFB) circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/AMPS applications. The IP2 calibrator is capable of providing different CMFB gain to tune its common-mode output impedance for each of the positive and negative mixer outputs. The CDMA mixer applying this method achieved a second-order input intercept point (IIP2) of 64 dBm, a third-order input intercept point (IIP3) of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. This result shows a 20 dB improvement from an uncalibrated IIP2 of 44 dBm. The receiver RFIC is implemented in a 0.5-/spl mu/m SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB.     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机.这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps.基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路.该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片.所测的接收机性能如下:噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV.该接收机采用1.8V电源电压,I,Q两路消耗的总电流为44mA.     

一种低噪声高线性度射频前端电路设计

介绍了超高频接收系统射频前端电路的芯片设计。从噪声匹配、线性度、阻抗匹配以及增益等方面详细讨论了集成低噪声放大器和下变频混频器的设计。电路采用硅基0.8μm B iCM O S工艺实现,经过测试,射频前端的增益约为18 dB,双边带噪声系数2.5 dB,IIP 3为+5 dBm,5 V工作电压下的消耗电流仅为3.4 mA。     

The MICROMIXER: a highly linear variant of the Gilbert mixer usinga bisymmetric Class-AB input stage

This paper outlines the basic theory of a development of the Gilbert mixer. The bipolar junction transistor (BJT) differential pair widely used as the RF input stage is replaced by a bisymmetric Class-AB topology based on translinear principles. It does not have inherent gain compression, affording a greatly extended signal capacity. The linearity of variants of the basic form is excellent, providing two-tone intermodulation intercepts as high as +30 dBm, without the expenditure of high bias currents. It can operate on supplies as low as 2.2 V, with a power consumption of under 5 mW. The input impedance of this mixer is accurately controllable (typically 50 Ω) and provides a true broadband match. The noise figure depends on design details and is generally not as low as in mixers specifically optimized for noise performance, although acceptable for many receiver applications. Inductively degenerated variants can be tuned to a narrowband match at microwave frequencies and provide full-mixing SSB noise figures as low as 6.5 dB, Practical realizations are in use in applications to 1.9 GHz     

2.5 V passive CMOS mixer with 20 dBm P1 dB compression

A passive CMOS downconversion mixer with LO buffer is presented in 0.25 μm SiGe BiCMOS using a 2.5 V supply. With a 60 MHz RF signal input, measurements show that the conversion loss is 2.9 dB, the input-referred 1 dB compression point is 20 dBm and the inputreferred noise is 2146.8 dBm/Hz. Compared to conventional NMOS mixers, the 1 dB compression point is improved by 9.7 dB. The tradeoffs and the design of the LO buffer, which has a strong impact on the intermodulation distortion, are also presented.     

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.     

A Low-Voltage Broadband Feedforward-Linearized BJT Mixer

A low-voltage, feedforward-linearized bipolar mixer realizes an input$hboxIP_3$of$+$14.3 dBm and an input$hboxIP_2$of$+$54.5 dBm at 2.4 GHz. Conversion (power) gain over the 1–6GHz RF input range is 12.4$,pm,$0.35 dB, while the input$hboxIP_3$is 13.6$,pm,$1.8dBm over the same frequency range. The broadband mixer's RF input impedance varies from 60.3-j7.1 at 2.4 GHz to 57.4-j16.6$~Omega$at 5.8GHz. Measured SSB (50$Omega$) noise figure is 18.6 dB at 2.4 GHz. No on-chip inductors are used in the design, and the 0.14$hbox mm^2$(active area) mixer dissipates 7.2 mW from a (minimum) 1.2 V supply.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

Second-order intermodulation mechanisms in CMOS downconverters

An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

Analysis and design of a low-voltage RF CMOS mixer

A CMOS low-voltage downconversion mixer is presented. With 1.69-GHz local oscillator signal input and 1.63-GHz RF signal input, measurement results show that the conversion gain is 6.631 dB, input-referred third-order intercept point is 1.51 dBm, single-sideband noise figure is 21.43 dB with a 1.8-V supply voltage. The mixer's noise and linearity analysis, layout technique to maximize RF performance and minimize noise performance are also presented in this paper.     

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively