Analysis of a SiGe MOSFET at 22nm

The present paper proposes a novel concept which can successfully reduce threshold voltage and increase switching speed of a conventional MOSFET. The proposed structures have been incorporated with a silicon germanium (SiGe) layer as a channel at the 22 nm technology node. Also, extensive analyses have been done to study the effects of replacing conventional polysilicon by graded dopent profile polysilicon, use of a high-k/silicon dioxide stack as a dielectric with graded dopent profile polysilicon and by using a high-k/silicon dioxide stack as a dielectric with a metal gate. Hafnium dioxide is used as a high-k material. Silvaco Athena and Atlas simulators are used for simulation as well as for finding electrical characteristics of the structures. For all the proposed structures two important parameters are studied in detail, threshold voltage and subthreshold slope. Comparing the three structures, it can be seen that using the high-k/silicon dioxide stack as a dielectric with a metal gate yields the best threshold voltage as well as good subthreshold slope which is directly related to the switching behaviour of the device. The required fabrication aspects of the modelled structures are also elaborated in detail.     

Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications

This work reports a platinum silicide (PtSi) Schottky Barrier (SB) p-MOSFET (SB p-MOSFET) using charge plasma concept for low power applications. Here, we use two different materials to form source of the device. The source consists of two parts as primary source and extension. To consist source, PtSi and for extension, platinum metal is used. The proposed device is named as charge plasma (CP) SB p-MOSFET (CP SB p-MOSFET). The use of platinum extension induces the hole plasma near the source end. As a result, increased band bending reduces the SB width. This enhances the DC performance of the device. In addition, we have compared the DC and analog/RF performance of both the proposed device and the conventional SB p-MOSFET. It is observed that the proposed device exhibits improvement in on-state current (I_on), on- to off current ratio (I_ON/I_OFF), transconductance (g_m), cut-off frequency (f_t), product of gain and bandwidth (f_a) and transconductance generation factor (g_m/I_ds). We also optimized the performance of the device by modulating the work function and length of metal employed for extension. Moreover, the proposed device eliminated the doping, lowers the thermal budget requirement and unaffected from fluctuations due to randomly distributed dopant.

     

An Accurate Model of Threshold Voltage and Effect of High-K Material for Fully Depleted Graded Channel DMDG MOSFET

Silicon - In this study, an accurate model for threshold voltage of graded channel dual material double gate (GCDMDG) structure metal-oxide-semiconductor (MOS) has been established and a...     

Enhancement of DC and Breakdown Performance on Single to Multi-Step Gate FP Using GaN-HEMT for High Power Applications

Silicon - AlGaN/GaN-HEMT with Single to Multi-step gate field plate is proposed in this work. The proposed device enhanced Drain current, breakdown voltage and shift in threshold voltage. The...     

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current–voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current–voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.     

Subthreshold Modeling of Graded Channel Double Gate Junctionless FETs

Silicon - In this paper, 2-D analytical models of channel central potential, threshold voltage, subthreshold current and subthreshold swing for graded channel double gate (GC-DG) Junctionless FETs...     

Improvement of Subthreshold Characteristics of Dopingless Tunnel FET Using Hetero Gate Dielectric Material: Analytical Modeling and Simulation

An improved subthreshold analytical model of Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) with stacked / hetero-dielectric gate oxide structure is proposed. The stacked gate oxide structure comprises of Silicon-dioxide (SiO₂) and Titanium Oxide (TiO₂). The high-K gate stack engineered device overcomes the Short Channel Effects (SCEs) caused by the ultrathin silicon devices. The subthreshold analysis is carried out by solving a two-dimensional Poisson’s equation using Parabolic approximation method. These characteristics are analyzed against various device parameters. Also, the impact of different high-K gate oxide materials with SiO₂ is also studied. A comparative analysis of short channel effects for DMDG TFET and DMDG JLTFET has been carried out. The results reveal that the proposed device provides better I_ON current, low leakage current and improved Transconductance-to-drain current ratio. Using TCAD Sentaurus device simulator, the subthreshold analytical model results have been simulated and verified with other TFET models.

     

Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions     

Fabrication of diamond in-plane-gated field effect transistors using oxygen plasma etching

Diamond dual in-plane-gated field effect transistors with very low gate leakage current have been fabricated on an undoped hydrogen-terminated diamond p-type surface using oxygen plasma etching. Adjusting the threshold voltage optimally by one side gate, lateral electric field from the other side gate modulates the channel conductance. The oxygen plasma etching of 60 nm in depth fully isolated the channel of the hydrogen-terminated diamond surface conductive layer from the side gates resulting very low gate leakage current (<1 pA at −60 V) at room temperature. This feature provides a necessary condition for the fabrication of diamond single-hole transistors operated at room temperature.     

A Novel Technique to Investigate the Impact of Temperature and Process Parameters on Electrostatic and Analog/RF Performance of Channel Modulated Junctionless Gate-all-around (CM-JL-GAA) MOSFET

Silicon - The channel modulated junctionless gate all around (CM-JL-GAA) MOSFET improves the SCE’s with high graded doping of the channel region. Temperature effects on electrostatic and...     

Memory effects of carbon nanotube-based field effect transistors

In this paper, we report the study on the non-volatile memory effects of carbon nanotube-based field effect transistors (CNTFETs), in which semiconducting single-wall carbon nanotubes (SWNTs) bridge the gold electrodes and the doped silicon substrate acts as the back gate. We find that our CNTFETs exhibit good performance with on/off ratio of more than 10⁴ and they also show strong memory effects. Hysteretic behaviors of the drain current as a function of the gate voltage are clearly observed at room temperature. The threshold voltage shift increases with increasing the sweeping range of the gate voltage. The CNTFET memory effects show good charge retention capability with the data storage time of around 7 days at ambient condition. Besides, the threshold voltage shift of the as-prepared CNTFETs is found to decrease with time and saturate after around 3 days. Water and alcohol molecules adsorbed on the carbon nanotube are suggested to be the origin of the phenomena. It is also observed that the threshold voltage shift in “top-contact” structures is larger than those in “bottom-contact” structures at the same gate voltage sweeping range.     

Surface-channel MESFET with boron-doped contact layer

In this investigation an attempt has been made to incorporate a high temperature stable refractory metal ohmic contact deposited onto an oxygen terminated contact area into the surface channel field effect transistor concept based on a H-terminated surface in the channel area. First transistors were fabricated. A drain current density of 75 mA/mm and a threshold voltage of V_th = −1.5 V was obtained for 1 µm gate length.     

Influence of Threshold Voltage Performance Analysis on Dual Halo Gate Stacked Triple Material Dual Gate TFET for Ultra Low Power Applications

Silicon - In this article, a two dimensional (2-D) threshold voltage modeling based gate and channel engineering are developed analytically for Dual Halo Gate Stacked Triple Material Dual Gate...     

基于金属浮栅层有机薄膜非易失性存储器的制备与表征

以聚甲基丙烯酸甲酯(PMMA)为栅介质,以并五苯为有机薄膜制备了有机薄膜非易失性存储器,研究基于热蒸发金属金浮栅层的存储行为。在2 s脉冲的偏压下,浮栅层通过充放电过程可导致明显的阈值电压偏移。在1 V的脉冲电压下可实现电荷的写入/擦除操作,在6 V的脉冲电压下可获得30.0 V的存储窗口。实验结果表明,基于金属浮栅层并以并五苯作为有机薄膜来制备非易失性存储器具有一定的研究价值和应用前景。     

Monolayer graphene/hexagonal boron nitride heterostructure

A buried metal-gate field-effect transistor (FET) using a stacked hexagonal boron nitride (h-BN) and chemically vapor deposited (CVD) graphene heterostructure is demonstrated. A thin h-BN multilayer serves as both gate dielectric and supporting layer for the monolayer graphene channel. It is observed that electrical stressing could significantly improve graphene conduction, similar to the effect reported in the graphene/SiO₂ system. In the graphene/h-BN/TiN FET structure, p-type doping behavior in graphene is observed, possibly attributed to spontaneous doping due to the work function difference between the graphene channel and the metal gate electrode. At a high-level of stress, graphene exhibits n-type doping behavior due to charge transfer across the thin h-BN multilayer. The dielectric strength and tunneling behavior of h-BN are investigated, showing the robust nature of the layer-structured insulator.     

Electrical Characteristics of 8-nm SOI n-FinFETs

This study is aimed at presenting the electrical characteristics of a nanoscale SOI n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Al₂O₃ as the dielectric material and their sensitivity to the number of fins and fin-thickness with 3C-SiC material in the channel region. In this work, the numerical simulation tool Silvaco-Atlas is used to simulate the device in three-dimensions and to extract new results concerning the electrical characteristics of the device at room temperature (300 K) in comparison to earlier generations. The threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, leakage current, on-current, and On/Off current ratio are analyzed. Simulation results show that the higher drain current and transconductance are obtained by increasing the number of fins. The use of a higher value of gate dielectric constant can increase the drain current and improve the leakage current. It is found that reducing the fin-thickness is beneficial in reducing the subthreshold slope, drain induced barrier lowering, and leakage current. It should be highlighted that the achieved results can be useful for further manufacturing processes.     

Ternary Logic Gates Using Quantum Dot Gate FETs (QDGFETs)

Quantum dot gate FETs (QDGFET) produce one intermediate state between two stable on and off states due to the change in the threshold voltage. A circuit model based on Berkeley Short-channel IGFET Model (BSIM) that accounts for this intermediate state is developed. Different ternary logics such as ternary logic inverter, MAX-MIN functions, multiplier, comparator, etc. can be implemented using QDGFETs. In this work the designs of ternary logic AND and OR gate based on QDGFET is introduced. Increased number of states in three state QDGFETs will increase the number of bit handling capability of this device and will help to handle more bits at a time with less circuit elements.     

3D modeling of dual-gate FinFET

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V_g1 >V_g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.     

Electrical properties of dye‐doped colour tunable organic light emitting diode

In this work, we report on the electrical properties of dye‐doped colour tunable organic light‐emitting diode (OLED). The device structure is glass substrate/indium tin oxide/N,N′‐di(naphthalen‐1‐yl)‐N,N′‐diphenyl‐benzidine (NPB) 30 nm/Alq₃:DCM 50 nm/Aluminum (Al) 150 nm where NPB is the hole transport layer. Alq₃:DCM is the emitting layer which made of tris(8‐hydroxyquinoline) aluminium (Alq₃) doped with 4‐(Dicyanomethylene)‐2‐methyl‐6‐(4‐dimethyl‐aminostyryl)‐4H‐pyran (DCM) organic dye. The influence of doping concentration has been investigated by current density–voltage measurement, luminance intensity–voltage characteristic, electroluminescence (EL) and impedance spectroscopy, respectively. The EL spectrum exhibits the shifted of peak position from green to red region. The threshold voltage of the device decreased at the low DCM doping concentration (1 wt.%), in contrast, when the increase in the doping concentrations then the threshold voltage will be increased. The highest luminance intensity and lowest turn‐on voltage of OLED can be observed at doping concentration about of 1 wt.% of DCM. The impedance characteristics of the dye‐doped OLED can be modelled by simply adopting the conventional equivalent circuit with the simple combination of resistors and capacitors network. © 2012 Canadian Society for Chemical Engineering     

Temperature-dependent electrical transport properties in graphene/Pb(Zr0.4Ti0.6)O3 field effect transistors

We report the temperature and gate voltage dependent electrical properties of PZT gated graphene field effect transistors (PZT-GFETs) in the vacuum atmosphere. The PZT-GFETs exhibit p-type characteristics which are attributed to the chemical doping induced the Fermi level shifting below the Dirac point. Meanwhile, it also shows a large memory window. The temperature dependencies of the source-drain current in the range of 20–300 K indicate thermally activated hysteresis behaviors. The hysteresis in the transfer characteristics of PZT-GFETs shows a simultaneous enlargement with increasing temperature. The hysteresis appears to stem from the screening of charges that are transferred from graphene to traps at the interface of PZT and graphene. The magnitude of the charge neutrality point under opposite gate voltage sweep are enhanced with the increase of temperature and gate voltage can be ascribed to the common effects of the temperature and voltage magnitude dependent mechanisms such as interface charge trapping process and the polarization effects of PZT films.