T-emitter bipolar power transistor with negative-temperature-gradient current gain

A PNP epitaxial-base power transistor with double diffused emitter (T-emitter) which exhibits a negative temperature gradient for ? is described. Qualitative analysis shows that a fall-off in ? with increase in temperature is a consequence of both the T-emitter geometry and the boron double diffused emitter area. Measurements on realised transistors give a mean value of d?/dt of ?0.25 at temperatures ranging from 20°C to 110°C.     

Effect of emitter-base spacing on the current gain of AlGaAs/GaAsheterojunction bipolar transistors

An investigation of the effect of surface recombination and emitter-base-contact spacing on the DC current-gain of AlGaAs/GaAs heterojunction bipolar transistor (HBT) using thin AlGaAs emitter structures is discussed. The selectively-etched, thin-AlGaAs-emitter layer has been used to prevent an exposed extrinsic base region, which has previously limited current gain because of high surface recombination. It is found that a factor of ~50 improvement in the current gain can be achieved by proper surface passivation and emitter-base-contact spacing     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

Accelerated reverse emitter-base bias stress methodologies andtime-to-failure application

A second current-acceleration method for measuring the reliability of silicon bipolar transistors under reverse emitter-base bias stress is demonstrated in this paper. The low-voltage operation condition in submicron transistors may be attained during the stress experiments, providing an accurate determination of the transistor's operation time-to-failure (TTF) without extrapolating from higher voltage stress data. Two different current-acceleration stress methods are demonstrated in one transistor design and compared with the traditional voltage-acceleration method using the carrier kinetic energy as the independent variable. It is shown that the traditional voltage-acceleration method can give an erroneous and larger extrapolated time-to-failure by several orders of magnitude in some devices     

Measurement of transistor high-frequency current gain

An approach commonly used in instruments to test the high-frequency current gain of transistors consists of driving the base with a calibrated current source and measuring the collector current with a very low resistance meter. The major shortcomings of such instruments are their insufficient accuracy and their limited range of quiescent test conditions. However, a thorough analysis of this method demonstrates the possibility of reducing the measurement error, in the most unfavorable case, to less than 4.5 per cent as well as the possibility of extending the test conditions to 10µv, 10µa. These improvements were obtained as a result of the development of such features as a source impedance of 50K Ω at 100 Mc, a collector load of 1 Ω and a very low capacitance socket.     

The emitter-base interface current in silicon bipolar transistorswith emitters deposited by plasma-enhanced CVD

The DC characteristics of bipolar devices with emitters deposited by the glow discharge of silane are discussed. The emitter material can be amorphous or single crystalline, grown by low-temperature plasma epitaxy. At deposition temperatures as low as 320°C, surface cleaning is the most critical step in the process. Results on different ex-situ and in-situ cleanings are included. A model for the base current of bipolar transistors which is in agreement with the observations is proposed. It is shown that the base-emitter interface limits the transistor performance. After optimization, diode ideality factors approaching unity are obtained     

Degradation of gain in bipolar transistors

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar h_FE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&T's 0.8 μm BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute h_FE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BV_EBO is deduced for constant voltage stress (V_stressEBO) conditions, confirming the importance of secondaries in the process of degradation     

hFEdegradation due to reverse bias emitter-base junction stress

Reverse bias stress of the emitter-base junction may degrade the hFEof a transistor when it is operated under normal bias conditions. The degradation mechanism exhibits no measurable temperature dependence and appears to be a surface effect. The junction characteristics exhibit no structure as a function of field plate voltage after stress. Pulse measurements indicate that the time required to induce degradation is less then 1.0 µs. Hot carriers appear to have an appreciable effect on the degradation. A mathematical model is presented to facilitate the comparison of degradation on devices with different initial current gains.     

Transport equations in heavily doped silicon,and the current gain of a bipolar transistor

The Fermi level and effective density of states are calculated for heavily doped silicon, using methods similar to those of Kleppinger and Lindholm and Van Overstraeten et al. For the case in which Boltzmann statistics can be applied to both types of carriers, modified transport equations are obtained in terms of two “heavy doping parameters,” which measure the magnitude and skewness of the effective forbidden band.These results are applied to the calculation of the d.c. current gain of a diffused bipolar transistor. We obtain reasonable current gain values without employing short carrier lifetimes, and our numerically calculated dependence of the current gain on injection level is reasonable. However, the quantitative accuracy of our calculations is limited by several factors.     

Theoretic curves of drift transistor current gain

Intrinsic common-base, short-circuit current gain analysis of drift transistors may be aided by means of a simplified approximation equation. The accuracy of the equation may be controlled by the investigator. A graphic solution for determining this parameter of moderate drift field transistors may be obtained by using the arcs of circles. The interrelation between the graphic analysis and the theoretic approximation provides a flexible yet accurate method of analyzing this parameter.     

Theoretical current gain of a cylindrical mesa transistor

For the cylindrical mesa transistor, computation of base-region transport efficiency is considered a boundary-value problem; solution of this problem yields mathematical equations applicable to the design and development of practical semiconductor devices. This analytical method is applied to the problem of minority-carrier transport across a solid-cylinder type structure which approximates the transistor base region. Minority-carrier losses—representing a fundamental limitation upon transistor-current gain—are introduced through an assumption of bulk and surface-recombination mechanisms.

Applications of this analysis are illustrated by establishing the common-emitter current gain for typical junction transistors. Assuming, in such computations, physical parameters approximating germanium and silicon diffused devices, the silicon transistor is shown to be less sensitive to surface recombination mechanisms. Further, the existence of an optimum emitter radius is demonstrated for a semiconductor structure similar to the cylindrical hook collector.     

Horizontal current bipolar transistor (HCBT): a new concept ofsilicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 μm technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n⁺ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices     

Base current relaxation transient in reverse emitter-base biasstressed silicon bipolar junction transistors

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO₂/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10^-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements     

Current gain of silicon bipolar transistor with polysilicon emitter contact

A two-region analysis is presented to predict the common-emitter current gain of a bipolar transistor with the polysilicon contact to the emitter for a case when the recombinations at the mono-poly interface are not negligible. The calculated current-gain enhancement for typical device parameters and for different values of interface recombination velocity show that the current-gain enhancement and its increase with decrease of emitter width is smaller for the interface with larger recombinations.     

Inverse current gain improvement of bipolar transistors by double-base diffusion

The double-base diffusion process is introduced and is experimentally shown to significantly improve the inverse or upward current gain of the n-p-n bipolar transistor. The technique consists of a deep p⁺diffusion into an external base region of multicollector transistors forming a close-in collar around the intrinsic base of each transistor. This technique, together with the use of deep diffusion n⁺guard rings around the complete unit cell, is shown to improve the inverse current gain significantly.     

Very high gain AlGaAs/GaAs pnp heterojunction bipolar transistor

The effect of the emitter Al mole fraction and emitter-base junction type on the performance of AlGaAs/GaAs pnp heterojunction transistors was investigated experimentally. A current gain as high as 1360 was obtained for a structure with an Al/sub 0.4/Ga/sub 0.6/As emitter and compositionally abrupt emitter-base junction; this was attributed to reduced surface recombination.<>     

Profiled current drive for pulsed bipolar transistor switching

Preliminary investigations have been made of the profiling of base current drive to obtain fast turn-on without lifetime pulse stretching and turn-off delays.<>     

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The <110> substrate is used for HCBT fabrication utilizing <111> crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.     

Lateral PNP GaAs bipolar transistor with minimized substrate current

Lateral pnp bipolar transistors have been fabricated using Be implantation to define the emitter and collector areas. The base area (1 - 2 µm wide) has been protected against Be ions during implantation by SiO2and photoresist. The lateral straggling and diffusion during the anneling process reduces the base width, which can be adjusted with the annealing temperature and time. Between the active n-GaAs layer and substrate, a n-Ga0.7Al0.3As layer is deposited. The Be ions penetrating the GaAs/GaAlAs interface form a pn junction in the GaAlAs layer below the emitter and collector area. This reduces the current by several orders of magnitude through the parasitic emitter-substrate (base) diode compared to a GaAs pn junction, due to the higher band gap. For these devices with an effective base width of 0.5 µm, a current gain of 10 in common emitter configuration has been obtained.     

High-level asymptotic variation of transistor base resistance and current gain

Using a finite-section model for bipolar transistors with current-dependent base resistance and gain, high-current asymptotic variations of base resistance, gain and effective emitter width are studied, and useful analytic formulas are presented.