Degradation of gain in bipolar transistors

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar h_FE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&T's 0.8 μm BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute h_FE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BV_EBO is deduced for constant voltage stress (V_stressEBO) conditions, confirming the importance of secondaries in the process of degradation     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2.5nm超薄栅短沟pMOSFETs在Vg=Vd/2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si-SiO2界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2 .5 nm超薄栅短沟p MOSFETs在Vg=Vd/ 2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si- Si O2 界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

Temperature dependence of the channel hot-carrier degradation ofn-channel MOSFET's

The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I_d-V_g characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping     

An alternative interpretation of hot electron interface degradationin NMOSFETs: isotope results irreconcilable with major defect generationby holes?

The giant deuterium isotope effect found previously for NMOS hot electron degradation is applied to study defect generation at the Si-SiO ₂ interface. The data suggest that interface defects related to hydrogen depassivation may be generated directly by channel hot electrons bombarding the interface without the necessity of injection into the oxide. This is in contrast to the standard teaching that energetic holes, created by impact ionization, and injected into the oxide are the main cause for hydrogen-related defect generation at the Si-SiO₂ interfaces     

A quantitative physical model for the band-to-bandtunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO₂ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled     

Hole current in dual dielectric under positive gate voltage

n-channel dual-dielectric transistors with SiO2:Si3N4gate insulators were fabricated with and without boron implant in the channel. Under positive gate voltage stress, electrons can enter the insulator from the silicon, and holes can enter the silicon from the insulator. The electrons and holes were measured by the technique described by Ginovker et al.[1]. For oxides thicker than 30 Å, it is always observed that the silicon hole current is 3-4 orders of magnitude below the silicon electron current. The physical origin of this hole current is shown to be field-enhanced excitation of electrons from the valence band to the conduction band in the silicon prior to entering the insulator, and is not due to the holes from the insulator entering the silicon.     

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel, thus substantially increasing channel hot electron energy. Measured hot electron gate current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten times more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

2DEG base hot electron transistors fabricated using MBE and in situion beam lithography

A vertical hot electron transistor incorporating a two-dimensional electron gas (2DEG) base has been fabricated in the GaAs-AlGaAs materials system. The difficulties caused by the need to form selective ohmic contacts to the different conducting layers have been overcome using a combination of in situ focused ion beam (FIB) isolation and molecular beam epitaxial (MBE) regrowth. This has allowed a high yield of working devices to be achieved with a typical common emitter current gain of h_FE=6 at low temperatures     

Hot-carrier current modeling and device degradation insurface-channel p-MOSFETs

The channel field and substrate current models developed for n-MOSFETs are applicable to p-MOSFETs. The impact ionization rate extracted for holes is found to be 8×10⁶ exp (-3.7×10⁶/E), where E is the electric field. The lucky electron approach was used to model the gate current of surface-channel (SC) p-MOSFETs successfully. Device degradation in p-MOSFETs is due to trapped electrons in the oxide. p-MOSFET lifetime has good correlation with gate current in SC p-MOSFETs. The correlation is better than with substrate current. I_G can be larger in a buried-channel (BC) p-MOSFET than in a comparable SC n-MOSFET. This makes the SC MOSFET a much more reliable device. Device lifetime of a p-MOSFET under pulse stress can be predicted from DC stress data for inverterlike waveforms. For other waveforms, there is an extra degradation probably caused by the excess hot carriers generated during the gate turn-off transient     

Effect of hot-carrier injection on n- and pMOSFET gate oxideintegrity

N- and pMOSFETs with 9-nm gate oxide are compared. Injected hot holes are about 100 times as effective as electrons at 10.5 MV/cm of oxide field in causing oxide breakdown. Gate current in nMOSFETs under stress conditions is due to holes and electrons. The gate current in pMOSFETs is about 1000 times as large, but solely due to electrons. PMOSFETs can tolerate 1000 times more charge injection than nMOSFETs, but not more drain current stress     

Hot electron and hot hole degradation of UHV/CVD SiGe HBT's

We investigate the degradation in current gain and low-frequency noise of SiGe HBT's under reverse emitter-base stress due to hot electrons (forward-collector stress) and hot holes (open-collector stress). Contrary to previous assumptions we show that hot electrons and hot holes with the same kinetic energy generate different amounts of traps and hence have a different impact on device degradation. These results suggest that the accuracy of using forward-collector stress as an acceleration tool and reliability predictor must be carefully examined. We also present, for the first time, the effect of Ge profile shape on the reliability of SiGe HBT's, as well as discuss measurements on SiGe HBT's as a function of device geometry and temperature     

薄栅氧化层相关击穿电荷

栅氧化层厚度的减薄要求深入研究薄栅介质的击穿和退化之间的关系 .利用衬底热空穴注入技术分别控制注入到薄栅氧化层中的热电子和空穴量 ,对相关击穿电荷进行了测试和研究 .结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .提出薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的新观点 .建立了 Si O2 介质击穿的物理模型并给出了理论分析     

薄栅氧化层相关击穿电荷

栅氧化层厚度的减薄要求深入研究薄栅介质的击穿和退化之间的关系.利用衬底热空穴注入技术分别控制注入到薄栅氧化层中的热电子和空穴量,对相关击穿电荷进行了测试和研究.结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡．提出薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的新观点.建立了SiO2介质击穿的物理模型并给出了理论分析.     

RF Frequency Doubling Using a Silicon p-i-n Diode-Based Mach–Zehnder Modulator

We demonstrate frequency doubling at 1 GHz using a new silicon Mach-Zehnder modulator (MZM). Modulation of the refractive index of silicon for an MZM action is achieved via the injection/depletion of electrons and holes in a p-i-n diode. The silicon MZM used in the experiment shows high phase-shift efficiency and a V_piL_pi of 1.88times10^-2Vldrcm which is nearly 350 times smaller than those of previously reported LiNbO₃-based MZM. Also, a theoretical analysis of frequency doubling in the time domain shows good agreement with the experimental results.     

Theoretical and experimental DC characterization of InGaAs-basedabrupt emitter HBT's

The DC characteristics of InP-InGaAs and InAlAs-InGaAs HBT's with abrupt emitter-base junctions are studied using a thermionic-field emission boundary-condition model. The model incorporates tunneling and thermionic emission into a one-dimensional drift-diffusion numerical scheme and accounts for breakdown and bulk recombination mechanisms. The effects of abrupt heterojunction transport and electrical junction displacement on the current gain h_FE and on the turn-on voltage are investigated. The simulations indicate that the spacer layer design has a profound effect on the DC behavior of these devices. A detailed performance comparison of different emitter structures indicates that InP-emitter HBT's show a more uniform h_FE than InAlAs-emitter HBT's especially at low current densities. Experimental data from a fabricated InAlAs-InGaAs abrupt emitter single HBT was compared to the theoretical predictions of the model. The analysis reveals that several injection and recombination mechanisms are responsible for the emitter-base forward characteristics. In the collector, the exact velocity-field profile and an anomalous multiplication factor are responsible for kinks in the output common-emitter characteristics and for soft breakdown of the collector-base junction     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

The Preparation of Nanocrystalline Silicon by Plasma-Enhanced Hydrogenation for the Fabrication of Light-Emitting Diodes

The fabrication of nanocrystalline silicon light-emitting diodes is reported using a novel plasma-enhanced hydrogenation method. The fabrication process consisted of the deposition of amorphous silicon on a silicon substrate, a hydrogen plasma treatment, and subsequent annealing, and the deposition of TiO₂, indium-tin oxide, and metal contact layers. The entire process was performed at temperatures below 400 degC and is compatible with standard silicon fabrication technologies. The current-voltage (I-V) characteristics of the device showed a rectifying diode behavior where electrons tunneled through the thin TiO₂ layer and recombined with the holes injected from the P-type silicon substrate leading to photon generation. The structure of the nanocrystalline silicon films was investigated by scanning electron and transmission electron microscopies, and the spectral distribution of the emitted light was measured by a cathodoluminescence