Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of design. It is illustrated in this paper that the WPM network can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Both, a system level analysis and circuit level verification of this WPM routing are presented in this paper. A multilevel interconnect network design simulator (MINDS) that uses system level interconnect prediction (SLIP) techniques and HSPICE circuit simulations for optimizing the interconnect dimensions has been used to assess the opportunities for application of WPM wire circuits in high performance digital designs. A custom routing example highlights the ease with which the WPM routing technique can be easily incorporated into the existing VLSI systems. In addition, for a 40 million transistor system case study, this system level analysis reveals that the use of a WPM network could result in an almost 20% decrease in the number of metal layers for less than 4% increase in dynamic power with no loss of communication throughput performance. The key virtues of WPM routing are its flexibility, robustness, implementation simplicity and its low overhead requirements.     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

Domino logic with variable threshold voltage keeper

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.     

Optical interconnects for neural and reconfigurable VLSIarchitectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits     

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective

Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to parameter variations. However, operating digital logic and memory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimizations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipation point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leakage current can be useful for other applications like thermal sensors.      

Generalized coupled interconnect transfer function and high-speedsignal simulations

A new expression for the coupled interconnect system transfer function has been derived under general linear generator and uncoupled load conditions, i.e., without any restrictions in circuit load impedance. High-speed-signals on coupled interconnects have been simulated using this transfer function. The simulation uses generalized interconnect circuit model parameters in which all line parameters are frequency dependent. The validity of the interconnect circuit parameters was confirmed previously using s-parameter measurements. High-speed signal simulation using this novel interconnect transfer function has been verified with time-domain measurements using an HP54121T high-speed sampling oscilloscope. This work accurately predicts coupled interconnect circuit responses. With this transfer function, signal integrity problems of high-performance VLSI circuits can be predicted in the design stage     

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

The proliferation of portable electronics has imposed a pressing need on design of low power circuits. Sub threshold circuits are the ideal candidate to quench the demand of ultra-low power. However, degraded performance and exacerbated variability are the major concerns of sub threshold circuits. Furthermore, the global interconnects significantly affects the performance and power dissipation in sub threshold circuits. The obvious reason is the increased capacitance of long global interconnects which is further augmented with increase in sub threshold CMOS driver resistance. This paper explores the performance of sub threshold global interconnect with six different configurations of DG FinFET driver circuit viz. FinFET SG, TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG. Performance analysis indicates that FinFET SG configuration exhibits 60.7, 0.8, 2.3, 37 and 40% better energy efficiency compared to TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG respectively at 225 mV supply voltage. Furthermore, the crosstalk analysis results shows that the glitch amplitude in TGSG driven interconnect and THYBRID driven interconnect is increased by 89.6 and 74% respectively compared to FinFET SG driven interconnect. This work also investigates the suitability of conventional buffer insertion technique for enhancing the performance of DG FinFET driven sub threshold global interconnects. The buffered and un-buffered interconnect shows comparable delay, PDP and EDP in sub threshold region. Furthermore, Monte Carlo analysis results indicate that spread in delay exhibited by FinFET SG driven un-buffered interconnect circuit is lesser by 25% compared to FinFET SG driven buffered circuit in sub threshold region.

     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Exponentially tapered H-tree clock distribution networks

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%.     

3-D ICs: a novel chip design for improving deep-submicrometerinterconnect performance and systems-on-chip integration

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined     

用于射频标签的低功耗上电复位电路

介绍了一种用于射频标签芯片中数字逻辑部分的上电复位电路。该上电复位电路适应于低电源电压的芯片,改变MOS晶体管的参数以及延迟时间可以调节脉冲的宽度和数字门电路加宽脉冲的宽度,通过反馈管,电路能够抵抗比较大的电源电压噪声影响。电路产生上电复位信号脉冲后,通过反馈控制使能端信号关断整个电路,实现低功耗。电路采用华虹NEC公司0.13μm标准CMOS工艺流片,测试结果表明,此电路能够输出有效的脉冲信号;脉冲过后的导通电流基本为0。FPGA平台的验证表明,芯片输出的POR信号能够正确启动标签中的数字基带芯片,输出信号有效。     

高性能微处理器中一种改进的高扇入多米诺电路设计与实现

设计实现了一种改进的高扇入多米诺电路结构.该电路的nMOS下拉网络分为多个块,有效降低了动态节点的电容,同时每一块只需要一个小尺寸的保持管.由于省去了标准多米诺逻辑中的尾管,有效地提升了该电路的性能.在0.13μm工艺下对该结构实现的一个64位或门进行模拟,延迟为63.9ps,功耗为32.4μw,面积为115μm2.与组合多米诺逻辑相比,延迟和功耗分别降低了55%和38%.     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

Efficient shield insertion for inductive noise reduction in nanometer technologies

With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The proposed algorithm determines the locations and number of shields needed to satisfy certain noise constraints. Experimental results show that the proposed approach minimizes the number of shields required to satisfy the noise constraints and uses less runtime than the best alternative reported approach.     

Transimpedance receiver design optimization for smart pixel arrays

Optical transimpedance receivers implemented in CMOS VLSI technologies are modeled and optimized for freespace optoelectronic interconnections. Sensitivity, bandwidth, power dissipation, and circuit area are analyzed for receivers using three different submicron CMOS processes. A comparison with the circuit noise limited optical power indicates that, for digital computing applications, the receiver sensitivity is limited by the gain-bandwidth product of the receiver amplifiers and the necessary noise margin of logic circuits     

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.     

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

A three-step method for the de-embedding of high-frequencyS-parameter measurements

The authors propose a general method of deembedding S-parameter measurements of the device-under-test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement. The DUT is the analog silicon bipolar junction transistor including the pad and interconnects. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters on the on-wafer open circuit which are taken from measurements of the short and through circuits. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (⩾10 GHz). A knowledge of the magnitude and type of parasitic deembedding circuit elements can aid the device engineer in the analysis of the error associated with deembedding