Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

The new two-dimensional electron gas base HBT (2DEG-HBT):two-dimensional numerical simulation

The bipolar/FET characteristics of the 2DEG-HBT are analyzed extensively by a two-dimensional numerical simulator based on a drift-diffusion model. For bipolar operations at high collector current densities, it is confirmed that the cutoff frequency f_T is determined mainly by the collector transit time of holes and by the charging time of the extrinsic base-collector capacitance C _bc^EXT. The charging times of the emitter and base regions and the base transit time are shown to be negligible. A high cutoff frequency F_T (88 GHz) and current gain h_FE (760) are obtained for an emitter size of 1×10 μm², and undoped collector thickness of 150 nm, and a collector current density J_c of 10⁵ A/cm². The FET operation of the same 2DEG-HBT structure shows a threshold voltage V_th of 0.74 V, the transconductance G_m^max of 80 mS/mm, and maximum cutoff frequency F_T^max of 15 GHz. The dependence of the device performance on material parameters is analyzed extensively from a device design point of view     

Polysilicon thin-film transistors with channel length and widthcomparable to or smaller than the grain size of the thin film

Poly-Si thin-film transistors (TFTs) with channel dimensions (width W, and length L) comparable to or smaller than the grain size of the poly-Si film were fabricated and characterized. The grain size of the poly-Si film was enhanced by Si ion implantation followed by a low-temperature anneal and was typically 1 to 3 μm in diameter. A remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L =2 μm. On the other hand, TFTs with submicrometer channel dimensions were characterized by an extremely abrupt switching in their I_D versus V_GS characteristics. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect of the device's floating body     

CW measurement of HBT thermal resistance

Measurements of the temperature dependence of β and V_BE were made on AlGaAs-GaAs HBTs and used to determine device thermal resistance. The measurements were CW and not switched or pulsed in order to have a simpler procedure. With base doping greater than 10¹⁹ cm^-3, HBTs have negligible base-width modulation (i.e., flat I_C versus V_CE characteristics) which makes CW thermal resistance measurement especially direct and simple     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Optimized silicon-rich oxide (SRO) deposition process for 5 V onlyflash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO₂ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO₂ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm² at J=0.1 A/cm² . The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices     

A multiple-state memory cell based on the resonant tunneling diode

The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I-V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V₀=0.27 V , V₁=0.42 V, and V₂=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V₀=0.35 V, V₁=0.42 V, V₂=0.54 V, and V ₃=0.59 V. A suggestion of an integrated device structure using this concept is also presented     

Novel GaAs/AlGaAs multiquantum-well Schottky-junction device andits photovoltaic LWIR detection

The authors have demonstrated photovoltaic detection for a multiple-quantum-well (MQW) long-wavelength infrared (LWIR) detector. With a blocking layer, the MQW detector exhibits Schottky I-V characteristics with extremely low dark current and excellent ideality factor. The dark current is 5×10^-14 A for a 100×100 μm² detector (designed for 10-μm response) at 40 K, nearly nine orders of magnitude lower than that of a similar MQW LWIR detector without the blocking layer. The ideality factor is ~1.01-1.05 at T=40-80 K. The measured Schottky-barrier height is consistent with the energy difference between first excited states and ground states, or the peak of spectral response. The authors also report a measured effective Richardson constant (A**) for a GaAs/AlGaAs heterojunction using this blocking layer structure. The A** is ~2.3 A/cm²/K ²     

On/off current ratio in P-channel poly-Si MOSFETs: dependence onhot-carrier stress conditions

Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V_GS=V_DS=-11 V, but can be increased by a factor of 50 for a stress bias of V_GS=-2 V, V_DS=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V_GS. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation     

Simulation of action potentials in a one-dimensional bidomain

An approximate method of calculating action potentials in a nerve fiber within a coaxial sheath is presented. The method is of the implicit type, but it avoids any large matrix inversion and is adapted to run conveniently on a small PC/AT. It produces traces of the extracellular voltage V_out, which is not calculated by other methods, as well as the intracellular potentials V_in. For homogeneous fibers with small sheath resistance, V_out is proportional to d² V_in/dz², as expected. In more complex cases, V_out remains small, but its shape is hard to predict. One such example is presented in which an extracellular voltage trace of novel shape is calculated     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern