A new approach to performance modelling of Client/Server distributed data base architectures

The recent technological advances in the field of computer and communication lead to distributed data base (DDB) architectures based on the Client/Server paradigm. Available DDB performance prediction methodologies are not sufficiently adequate being too expensive both in the model definition and in the model analysis because of the structural complexity and the large system dimension.

This paper concentrates on a new approach to performance modeling of DDB systems called “independent modelling approach”. This approach separates the DDB software model from the DDB machinery model, and models from solution techniques. This way the aspects related to data contention can be analysed as a pure software characteristic and separated from resource contention, considered as a machinery characteristic. Furthermore, it is possible to analytically model some system aspects (e.g., the software only, or part of it, without involving the machinery model), and apply combined analytical/simulation methods for the remaining system aspects. This results in higher flexibility at lower computational cost in the performance analysis of complex DDB architectures.

A case study is developed and experimental results are discussed to show the effectiveness of the approach.     

Parallel algorithms for model reduction of discrete-time systems

Computing reduced-order models of controlled dynamical systems is of fundamental importance in many analysis and synthesis problems in systems and control theory. Algorithmic aspects of model reduction methods based on state-space truncation for linear discrete-time systems are addressed here. In contrast to the often-used approach of applying methods for continuous-time systems to discrete-time models employing a bilinear transformation, we devise special algorithms for discrete-time systems. Usually, this is more reliable and efficient. All methods discussed require in an initial stage the computation of the Gramians of the system. Using an accelerated fixed-point iteration for computing the full-rank factors of the Gramians yields some favorable computational aspects, particularly for non-minimal systems. The computations only require efficient implementations of basic linear algebra operations readily available on modern computer architectures. We discuss aspects of the parallel implementation of these methods and show the performance and scalability on distributed memory computers. Our approach enables users to deal with very complex systems using relatively cheap infrastructure, as, for example, a local PC or workstation network.     

A new system architecture for crowd simulation

Crowd simulation requires both rendering visually plausible images and managing the behavior of autonomous agents. Therefore, these applications need an efficient design that allows them to simultaneously handle these two requirements. Although several proposals have focused on the software architectures for these systems, no proposals have focused on the computer systems supporting them.In this paper, we analyze the computer architectures used in the literature to support distributed virtual environments. Also, we propose a distributed computer architecture which is efficient enough to support simulations of thousand of autonomous agents. This proposal consists of a cluster of interconnected computers in order to improve flexibility and robustness, as well as a hierarchical software architecture that efficiently provides consistency. Performance evaluation results show that the trade-off between flexibility and consistency allows to efficiently manage thousands of autonomous agents. Therefore, this network-based system architecture can provide the required scalability for large-scale crowd simulations.     

基于组件的嵌入式软件开发中的几个关键问题

针对嵌入式系统的实际特性,着重从系统的角度提出构造一个嵌入式应用程序的开发架构,也可以称为开发框架.该开发架构是以基于组件的方法来开发嵌入式应用程序的,其主要研究系统结构规约、系统行为规约、组件配置和执行、程序产生和系统配置等几个关键问题.研究的结果将指导一个分布嵌入式应用程序开发框架的构造.     

Embedded software debugging using virtual filesystem abstractions

We present a scalable technique to simplify the software debugging process for embedded systems that is based on the use of distributed filesystem abstractions. In this technique, the principal building blocks within embedded systems comprising “system-on-chip” (SoC) devices export debugging interfaces realized with filesystem abstractions. These filesystem interfaces are composed in a manner consistent with the hardware hierarchy and provide a portable interface to concurrently debug software executing in the various processing elements within the embedded system. We illustrate application of the model to support the various software debugging requirements unique to SoCs, many of which traditional methods are ill-equipped to deal with. We also present an architecture that may be used to realize distributed filesystem abstractions within resource constrained embedded architectures.     

Using database machines in embedded computer systems

A discussion whether or not present database machine technology addresses the needs of embedded computer systems is presented. The interface between the embedded system and its environment tends to be complex, asynchronous, highly parallel and sometimes distributed. In addition, embedded systems are likely to have stringent resource requirements, both physical and logical. An answer to both the complexity issue and the resource limitation can be potentially found in the database machine.Functions are identified for two applications that the embedded system in general and the database machine specifically are asked to perform. Given the requirements of such applications the current database machine technology is evaluated.Finally, given the primary requirements of data security and system throughput of tactical embedded computer systems, a database machine using distributed architecture is proposed. The system has the potential for connecting multiple database machines to each host or for connecting multiple hosts to one database machine.     

Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems

In order to satisfy the needs for increasing computer processing power, there are significant changes in the design process of modern computing systems. Major chip-vendors are deploying multicore or manycore processors to their product lines. Multicore architectures offer a tremendous amount of processing speed. At the same time, they bring challenges for embedded systems which suffer from limited resources. Various cache memory hierarchies have been proposed to satisfy the requirements for different embedded systems. Normally, a level-1 cache (CL1) memory is dedicated to each core. However, the level-2 cache (CL2) can be shared (like Intel Xeon and IBM Cell) or distributed (like AMD Athlon). In this paper, we investigate the impact of the CL2 organization type (shared Vs distributed) on the performance and power consumption of homogeneous multicore embedded systems. We use VisualSim and Heptane tools to model and simulate the target architectures running FFT, MI, and DFT applications. Experimental results show that by replacing a single-core system with an 8-core system, reductions in mean delay per core of 64% for distributed CL2 and 53% for shared CL2 are possible with little additional power (15% for distributed CL2 and 18% for shared CL2) for FFT. Results also reveal that the distributed CL2 hierarchy outperforms the shared CL2 hierarchy for all three applications considered and for other applications with similar code characteristics.     

The NEXUS open system for integrating robotic software

In this paper a framework for constructing flexible, robust and efficient software applications for robots is described. The basic concepts needed to integrate complex, multidisciplinary robot software architectures are identified, and the methods to achieve them are taken from different areas of research (programming languages, network communication systems, real-time systems, etc.). The result is an open software system called NEXUS which includes the basic characteristics needed for the integration of very different software modules, minimizing the effort of integration and maximizing the reusability, efficiency and robustness of the resulting software applications. This software has proven to be a basis for more sophisticated tools that help in reducing the cost of modifications to and the complexity of multidisciplinary projects, allowing highly structured and reusable designs to be implemented. Although it has been currently implemented for mobile robots, it is a sufficiently generic framework suitable for use in other control systems.     

矿用救援机器人控制体系结构研究

讨论了矿用救援机器人的工作环境及其控制体系结构的性能要求;介绍了目前已有的矿用救援机器人控制体系结构,包括基于工控机的闭式控制体系结构、基于PLC的分布式控制体系结构、基于工控机的分布式控制体系结构及基于嵌入式系统的分布式控制体系结构,分析了各种体系结构的优缺点;提出了一种基于嵌入式系统和CAN总线的分布式控制体系结构。该控制体系结构比目前已有的控制体系结构能更好地适应煤矿井下复杂的环境,特别适用于煤矿灾后救援。     

分布嵌入式应用开发平台eBus

嵌入式系统领域对分布嵌入式应用的需求越来越大,但采用传统开发分布嵌入式应用的花费巨大。同时,CORBA的出现极大地提高了分布式应用的开发效率,它的许多优点也非常适用于分布嵌入式系统,但CORBA不是针对嵌入式系统提出的,存在一些不适合嵌入式系统的方面。eBus是一个针对嵌入式系统而设计的高效、可配置的embedded CORBA产品。本介绍了eBus的系统框架,并以网络管理应用为例,说明了如何应用eBus开发分布的嵌入式系统。     

Software Reliability

During the last decade there have appeared in the literature many contributions on the reliability aspects of computer hardware, but relatively few on software. We see this balance changing as software is now becoming the most expensive and complex item in a computer installation. This situation is intensifying as applications become more sophisticated, as larger teams are required to produce the software, and as software mistakes that enter operational systems become more costly. We believe that this condition will be remedied when tools as powerful as those available for ensuring the reliability of hardware become available for software.     

计算机系统在自动化仪器仪表中的应用

随着各领域技术的迅速发展和不断进步,计算机技术逐渐渗透到自动化控制技术中,其中,嵌入式计算机系统已经在仪器仪表领域获得了越来越多的应用。如今,自动化仪器仪表已具备＂工业IT＂的特征。本文首先介绍了我国仪器仪表控制系统的发展历程,阐述了嵌入式计算机系统的定义、特征、基本构架以及嵌入式计算机系统中的软件技术,对嵌入式计算机系统在仪器仪表中的应用进行了研究与分析,并展望了高级嵌入式系统对未来新型仪器仪表技术的支持及其前景。     

An open platform for developing multiprocessor SoCs

Nanometer technologies integrate hundreds of millions of transistors in a single chip. Opportunities provided by these technologies, combined with the consolidation of platform-based design approaches, the evolution toward multiprocessor architectures, and consideration of the network-on-chip (NoC) paradigm suggest new methods for designing and verifying embedded systems. Clearly, a pure software simulation platform can't provide the performance required for developing multiprocessor system-on-chip (MPSoC) designs. One of the main design risks for today's systems is the architecture, which developers must validate as early as possible in the overall system design cycle because it has the biggest impact on system dimensioning and performance. To solve these problems, we've studied a reconfigurable MPSoC emulation platform and developed the main emulation subsystem and board. A low-cost modular approach that uses emulation offers an alternative to software simulation for the design and verification of complex multiprocessor system-on-chip (MPSoC) designs.     

A partitioning algorithm for distributed software systems design

One complication in using distributed computer systems is the increased complexity of developing distributed software systems. These software systems are composed of asynchronously executing components which communicate via message passing. Current software design techniques are not adequate for use in the design of distributed software systems. New design methods which explicitly address the problem of system partitioning are needed. An overall distributed software design approach is presented. The key to the design approach is the presentation of a distributed processing component (DPC) partitioning algorithm for clustering functional modules in order to derive a set of distributed processing components. The design approach is oriented towards producing a software system which is hierarchical, which exploits potential concurrency that exists between functional modules, and which avoids nonprofitable message traffic.     

High performance real-time scheduling of multiple mixed-criticality functions in heterogeneous distributed embedded systems

The architectures of high-end embedded system have evolved into heterogeneous distributed integrated architectures. The scheduling of multiple distributed mixed-criticality functions in heterogeneous distributed embedded systems is a considerable challenge because of the different requirements of systems and functions. Overall scheduling length (i.e., makespan) is the main concern in system performance, whereas deadlines represent the major timing constraints of functions. Most algorithms use the fairness policies to reduce the makespan in heterogeneous distributed systems. However, these fairness policies cannot meet the deadlines of most functions. Each function has different criticality levels (e.g., severity), and missing the deadlines of certain high-criticality functions may cause fatal injuries to people under this situation. This study first constructs related models for heterogeneous distributed embedded systems. Thereafter, the criticality certification, scheduling framework, and fairness of multiple heterogeneous earliest finish time (F_MHEFT) algorithm for heterogeneous distributed embedded systems are presented. Finally, this study proposes a novel algorithm called the deadline-span of multiple heterogeneous earliest finish time (D_MHEFT), which is a scheduling algorithm for multiple mixed-criticality functions. The F_MHEFT algorithm aims at improving the performance of systems, while the D_MHEFT algorithm tries to meet the deadlines of more high-criticality functions by sacrificing a certain performance. The experimental results demonstrate that the D_MHEFT algorithm can significantly reduce the deadline miss ratio (DMR) and keep satisfactory performance over existing methods.     

嵌入式API测试套生成方法和技术

随着嵌入式计算机系统应用的不断扩展,嵌入式系统的可靠性引起了学术界和工业界的广泛关注,也提出了很多增进可靠性的方法和技术.然而,现有的方法和技术在测试套生成方面论述不多,所以在处理大批量嵌入式系统测试工作中遇到了挑战.讨论抽象测试套生成方法和适配技术,提出了LTS(labeled transition system)到BT(behavior tree)的转换算法,从而使TTCN(test and testing control notation)测试套可以通过转换嵌入式软件的LTS描述产生.还介绍了基于上述转换算法的嵌入式软件测试工具包,以及一个嵌入式物联网识读器测试案例研究.