Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

Effects of high-κ gate dielectric materials on metal andsilicon gate workfunctions

The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-κ dielectrics differ appreciably from their values on SiO₂ or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO₂, Si₃N₄, ZrO₂, and HfO ₂ are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-κ gate dielectrics     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

Carrier transport mechanism in La-incorporated high-k dielectric/metal gate stack MOSFETs

In this paper, carrier transport mechanism of MOSFETs with HfLaSiON was analyzed. It was shown that gate current is consisted of Schottky emission, Frenkel-Poole (F-P) emission and Fowler-Nordheim (F-N) tunneling components. Schottky barrier height is calculated to be 0.829 eV from Schottky emission model. Fowler-Nordheim tunneling barrier height was 0.941 eV at high electric field regions and the trap energy level extracted using Frenkel-Poole emission model was 0.907 eV. From the deviation of weak temperature dependence for gate leakage current at low electric field region, TAT mechanism is also considered.     

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.     

Effects of gate geometry on propagation delay of integrated injection logic (I/SUP 2/L)

The effects of gate geometry on the propagation delay have been investigated for I/SUP 2/L gates with a self-aligned double-diffusion injector (S/SUP 2/L). To improve the switching speed of the I/SUP 2/L gate, the stored charge in the upside-down operated n-p-n transistor in the gate should be minimized. Following this principle, one can straightforwardly find that the reduction of the stored charges in the internal n-p-n base region and in the lateral p-n-p base region is the step to be taken for the further improvement of the speed. This can be realized by simply contracting the geometry of the gate. The minimum delay time realized in the gate was 3.2 ns/gate. Assuming that capabilities of processing the devices with 1-/spl mu/m accuracy become available, it is predicted that 1 ns/gate delay time can be realized with an improved S/SUP 2/L gate.     

Research on the hydrogen terminated single crystal diamond MOSFET with MoO3 dielectric and gold gate metal

The single crystal diamond with maximum width about 10 mm has been grown by using microwave plasma chemical vapor deposition equipment.The quality of the grown diamond was characterized using an X-ray diffractometer.The FWHM of the (004) rocking curve is 37.91 arcsec,which is comparable to the result of the electronic grade single crystal diamond commercially obtained from Element Six Ltd.The hydrogen terminated diamond field effect transistors with Au/MoO3 gates were fabricated based on our CVD diamond and the characteristics of the device were compared with the prototype Al/MoO3 gate.The device with the Au/MoO3 gate shows lower on-resistance and higher gate leakage current.The detailed analysis indicates the presence of aluminum oxide at the Al/MoO3 interface,which has been directly demonstrated by characterizing the interface between Al and MoO3 by X-ray photoelectron spectroscopy.In addition,there should be a surface transfer doping effect of the MoO3 layer on H-diamond even with the atmospheric-adsorbate induced 2DHG preserved after MoO3 deposition.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

Electrical method of measuring physical thickness and nitrogen concentration of silicon oxynitride gate dielectric for MOSFETs

This paper proposes an electrical method of measuring the physical thickness T_ox and the nitrogen concentration α_N of the silicon oxynitride (SiON) gate dielectric for MOSFETs. The proposed method uses the facts that the gate dielectric breakdown field strength E_BD depends on α_N for a given T_ox and the direct tunneling (DT) current depends strongly on T_ox. Gate current I_g versus gate voltage V_g (I_g-V_g) curves at a given α_N were calculated for different T_oxs using the DT model, and measurements were compared to the curves to obtain T_ox. The α_N was obtained by comparing the measured E_BD at a given T_ox with the theoretical E_BD for a SiON gate dielectric. These two steps were iterated until the convergence error of α_N was less than 1%. The I_g-V_g curves calculated using the extracted T_oxs and α_Ns agreed very well with measurements when V_g was less than the gate breakdown voltage. The difference between the equivalent oxide thickness (EOT) measured using the C-V method and the EOT calculated using the extracted T_ox and α_N was less than 7%, demonstrating that the proposed method can accurately determine T_ox and α_N of an ultra-thin SiON gate dielectric from only the measured I_g-V_g curve of the MOSFET.     

Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness down to 1.9 nm are discussed.     

The properties of high-k gate dielectric films deposited on HRSOI

In this paper, HfO₂ dielectric films with blocking layers (BL) of Al₂O₃ were deposited on high resistivity silicon-on-insulator (HRSOI), and the interfacial and electrical properties are reported. High-resolution transmission electron microscopy (HRTEM) indicated that BL could thin the interfacial layer, keep the interface smooth, and retain HfO₂ amorphous after annealing. Energy dispersive X-ray spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) confirmed that BL weaken Si diffusion and suppressed the further growth of HfSiO. Electrical measurements indicated that there was no hysteresis was observed in capacitance–voltage curves, and Flatband shift and interface state density is 0.05 V and −1.3 × 10¹² cm⁻², respectively.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

衬底热空穴导致的薄栅介质经时击穿的物理模型研究

该文定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化,首次提出了薄栅氧化层的经时击穿是由热电子和空穴共同作用的结果,并对上述实验现象进行了详细的理论分析,提出了薄栅氧化层经时击穿分两步。首先注入的热电子在薄栅氧化层中产生陷阱中心,然后空穴陷入陷阱导致薄栅氧击穿。     

Optical control of millimeter-wave propagation in dielectric waveguides

We have demonstrated a new method for controlling millimeter-wave propagation in semiconductor waveguides-optical control. Phase shifts as high as 300°/cm at 94 GHz were observed accompanied by less than 1 dB insertion loss. A theoretical model has been developed to account in detail for the observed behavior. Extension of this technique to ultra-fast switching and gating of millimeter-wave signals is also described. Millimeter-wave pulsewidths as short as 1 ns and variable to tens of nanoseconds can readily be obtained.     

Modal analysis of nonlinear propagation in dielectric slabwaveguide

In this paper we present a study of nonlinear guided propagation based on the development of the actual electromagnetic field in terms of the modes of a linear dielectric guide. This approach permits in principle to consider propagation over finite lengths of waveguide of general nonuniform nonlinearity, with arbitrary excitation at a finite location and to retain the second derivative term that is neglected in the usual Schrodinger equation approximation to the wave equation