基于光照-反射模型的图像增强算法的FPGA设计

针对视频图像增强处理的应用需求及视频图像场景的多样化特点,给出了一种基于光照-反射模型的低照度图像增强算法及其硬件实现。首先,基于光照-反射模型将亮度图像分解为照度分量、反射分量,并对估计的照度分量进行非线性调节,合成新的亮度图像;然后,引入调整系数对光照估计进行场景补偿以适应不同的场景;最后,在现场可编程逻辑门阵列(FPGA)硬件上进行算法实现。在Altera EP4CE40F23C8 FPGA硬件上实现结果表明,图像增强算法的主、客观处理效果得到明显提升,可满足不同场景的低照度视频图像实时增强处理应用。     

双处理器实时视频拼接系统

当一些视频系统需更大观测范围,同时获得完整场景是一个问题.针对这种情况,提出一套基于FPGA和DSP双处理器协同工作的视频拼接系统,设计了包括双处理器、FLASH程序存储器、SDRAM数据存储器、SRAM数据存储器、视频AD和视频解码器等硬件结构.系统采集两路视频信号输入,对其进行数字视频转换,然后由FPGA做基本图像处理,并将其送入SDRAM进行存储.DSP将初步处理后的图像数据取出,并对其进行图像配准和图像融合.为了保证图像的实时性,系统采用实时高效易实现的改进的PSO算法实现图像配准,采用平均加权法实现图像融合.实验结果表明,此系统可对两幅720×576分辨率、25帧/秒的视频图像进行实时拼接,满足所需大视场视频图像要求.     

基于FPGA的视频滤波处理系统

介绍一个以XC2S200为核心的视频信号滤波处理系统,该系统为水下图像目标识别和监控提供了一种解决方案,它采用共轭算法对图像进行统一、高效的全局变换,滤波增强效率更高,并且采用Xilinx公司的FPGA芯片XC2S200位处理核心,使得该系统结构紧凑,配置灵活,便于携带。该系统可实时使水下昏暗、模糊的视频图像获得较好的噪声滤波效果,并输出给液晶显示器显示。可应用于水下场景监测或监控,具有很好的市场应用前景。     

FPGA软硬件协同处理实时图像处理系统

基于PC机图像处理系统实时性不强,DSP+FPGA图像处理系统的成本高、资源利用率低,单纯使用FPGA硬件实现的图像算法类型较为单一,针对这一系列问题,提出了一种基于FPGA软硬件协同处理的实时图像处理系统.采用一片FPGA芯片作为系统的核心,利用CCD相机等采集图像,通过SSRAM将图像缓存,以SOPC为控制核心,协调软硬件共同进行图像处理.易于使用硬件实现的图像处理模块(如滤波、形态学算法、图像校正、边缘检测等)均使用Verilog HDL语言实现,通过SOPC控制这些图像处理模块,实现相应的图像处理功能;而硬件难于实现的部分(如流程控制、复杂的分支判断)则使用SOPC中的CPU来实现.实验表明,系统卖时性强、图像处理速度快、可进行复杂图像算法的运算,同时具有设计简单、应用灵活、成本低的特点.     

基于自适应噪声模型和线积分卷积的铅笔画模拟

提出一种铅笔画模拟的方法.和传统的铅笔画步骤类似,经过轮廓提取和色调合成,产生铅笔画模拟图像.轮廓提取通过L0平滑后,用四向索贝尔算子提取边界,借助线积分卷积实现色调合成.与现存方法不同的是,给出一种自适应噪声模型,根据源图像产生自适应的噪声,将其作为线积分卷积的输入图像.实验证明提出的方法可以用来产生具有艺术效果的铅笔画模拟图像.     

基于嵌入式机器视觉的多瓶口缺陷检测系统设计

目的 为了解决瓶口质量人工检测效率低且不稳定的问题。方法 采用HD-SDI的高清视频图像技术设计一种基于频率为70 MHz的STM32硬件检测系统,通过对视频读入、256 MB存储、29.97帧的视频输入输出和报警等硬件电路的设计,基于此搭建视频处理主流程、通信程序和图像处理的一系列软件算法来实现瓶喉口的缺陷检测,通过单张相片中塑料瓶口边缘轮廓来对比分析系统的可靠性。结果 实验证明,系统可以在0.26 s内识别1个瓶口,生产线产出速度为2.4 s/个。结论 该系统可以稳定、实时地检测多个瓶体口缺陷效果。     

人眼微动机制实时红外图像边缘提取

图像边缘特征提取是视频跟踪和目标提取的关键步骤,其性能和处理时间直接影响了后续图像处理的性能及视觉系统的整体响应时间.本文研究了一种基于人眼固视微动的实时图像边缘提取算法,针对算法具有边缘识别能力强,但运算量大的特点.通过采用并行处理结构及流水线技术在FPGA内实现了该算法,试验结果说明该算法在FPGA内实现具有与视频流同步的实时性,并且边缘提取的效果很好.在图像目标实时跟踪系统中应用,极大提高了目标的跟踪精度和稳定性.     

面向格式转换的数字视频处理方法及其硬件实现

视频格式转换是当前数字化处理电视和新一代的全数字电视中的一项重要的技术。把具有图像边缘保持特性的降噪滤波器与运动自适应的逐行插补算法相结合,提出一种新的视频格式转换算法,并进一步讨论该算法硬件实现的原理和结构。中所提出的算法已用FPGA芯片实现,实验结果表明该算法十分有效。     

基于TMS320DM642的疲劳检测系统硬件设计

为了解决因疲劳/瞌睡驾驶而造成的交通事故，研究了各种疲劳检测算法。针对疲劳检测算法中大数据量、高速传输、复杂运算的实际需要，设计了以SAA7115 为视频采集AD，DSP器件TMS320DM642为核心处理器，SAA7105为视频输出DA，利用FPGA控制输出，以实现增强显示功能的实时视频处理系统。该系统可以满足多路视频的实时采集、处理、显示的需求，可以作为疲劳检测算法的硬件平台，同时也可以作为视频处理、图像处理的硬件平台。     

浅谈图像视频处理技术

图像视频处理是根据图像处理算法对图像视频进行相应的处理。目前图像视频处理技术已经在我们的生活中应用得十分广泛,其主要包括智能分析处理技术、视频透雾增透技术、数字图像宽度动态的算法以及超分辨率重建技术。该文将通过对图像视频处理技术的了解,分析其在生活中的应用,进一步了解在新时代图像视频处理技术有何新突破,旨在为相关人员提供一定的借鉴。     

FPGA Implementation of Deep Leaning Model for Video Analytics

In recent years, deep neural networks have become a fascinating and influential research subject, and they play a critical role in video processing and analytics. Since, video analytics are predominantly hardware centric, exploration of implementing the deep neural networks in the hardware needs its brighter light of research. However, the computational complexity and resource constraints of deep neural networks are increasing exponentially by time. Convolutional neural networks are one of the most popular deep learning architecture especially for image classification and video analytics. But these algorithms need an efficient implement strategy for incorporating more real time computations in terms of handling the videos in the hardware. Field programmable Gate arrays (FPGA) is thought to be more advantageous in implementing the convolutional neural networks when compared to Graphics Processing Unit (GPU) in terms of energy efficient and low computational complexity. But still, an intelligent architecture is required for implementing the CNN in FPGA for processing the videos. This paper introduces a modern high-performance, energy-efficient Bat Pruned Ensembled Convolutional networks (BPEC-CNN) for processing the video in the hardware. The system integrates the Bat Evolutionary Pruned layers for CNN and implements the new shared Distributed Filtering Structures (DFS) for handing the filter layers in CNN with pipelined data-path in FPGA. In addition, the proposed system adopts the hardware-software co-design methodology for an energy efficiency and less computational complexity. The extensive experimentations are carried out using CASIA video datasets with ARTIX-7 FPGA boards (number) and various algorithms centric parameters such as accuracy, sensitivity, specificity and architecture centric parameters such as the power, area and throughput are analyzed. These results are then compared with the existing pruned CNN architectures such as CNN-Prunner in which the proposed architecture has been shown 25% better performance than the existing architectures.     

基于FPGA的水溶膜生产裂纹图像识别

目的针对水溶膜(PVA)生产中出现的问题,设计一种基于FPGA的水溶膜裂纹图像检测系统,实现生产中产品质量的及时反馈。方法结合FPGA自身的优点构建系统硬件组成,设计与之相匹配的图像采集、数据存储、图像处理、图像显示等功能模块。对灰度变换、图像分割等传统图像处理算法进行优化,利用Xilinx公司的ISE软件在System Generator软件平台上对设计做仿真实验,将采集到的水溶膜裂纹图像进行图像处理,通过识别到的水溶膜质量缺陷来验证设计方案的可行性。结果仿真及实验表明,FPGA可以利用高速的数据并行处理方式来进行图像处理,并应用于水溶膜裂纹图像识别。结论该系统为水溶膜裂纹的自动识别提供了新的途经,具有一定的市场价值。     

A single FPGA-based portable ultrasound imaging system for point-of-care applications

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.     

RETRACTED: Implementation System of Human Eye Tracking Algorithm Based on FPGA

With the high-speed development of transportation industry, highway traffic safety has become a considerable problem. Meanwhile, with the development of embedded system and hardware chip, in recent years, human eye detection eye tracking and positioning technology have been more and more widely used in man-machine interaction, security access control and visual detection.
In this paper, the high parallelism of FPGA was utilized to realize an elliptical approximate real-time human eye tracking system, which was achieved by the series register structure and random sample consensus (RANSAC), thus improving the speed of image processing without using external memory. Because eye images acquired by the camera often generate a lot of noises due to uneven light and dark background, the preprocessing technologies such as color conversion, image filtering, histogram modification and image sharpening were adopted. In terms of feature extraction of images, the eye tracking algorithm in this paper adopted seven-section rectangular eye tracking characteristic method, which increased a section between the mouth and the nose on the basis of the traditional six-section method, so its recognition accuracy is much higher. It is convenient for the realization of hardware parallel system in FPGA. Finally, aiming at the accuracy and real-time performance of the design system, a more comprehensive simulation test was carried out.
The human eye tracking system was verified on DE2-115 multimedia development platform, and the performance of VGA (resolution: 640×480) images of 8-bit grayscale was tested. The results showed that the detection speed of this system was about 47 frames per second under the condition that the detection rate of human face (front face, no inclination) was 93%, which reached the real-time detection level. Additionally, the accuracy of eye tracking based on FPGA system was more than 95%, and it has achieved ideal results in real-time performance and robustness.     

基于Zynq的实时视频图像角点检测系统

针对机器视觉测量应用中,待测关键点的自动识别与定位中的角点信息提取问题,以ZYNQ系列可拓展平台内部ARM+FPGA的异构架构为基础,采用软硬件协同设计方法,搭建了一套可进行实时视频图像角点检测的系统。利用Vivado HLS工具,将角点检测算法封装成可以部署到PL端的IP核,极大地缩短了开发周期;对系统中各个模块进行了合理的任务分配,使得系统拥有ARM的灵活性以及FPGA的并行处理能力,展现了并行异构架构的优势。该系统中图像算法IP核可以进行灵活的算法替换和更新,为基于机器视觉检测的小型化应用提供了重要参考。     

NAND Flash 图像记录系统底层写入控制技术

为提高图像记录系统中 NAND flash 阵列的存储带宽,分别研究和实现了 NAND flash 的片内交叉写入、片内并行写入和片内交叉并行写入控制技术,在此基础上提出了片内交叉写入和片外2级流水线结合的写入方法,该方法利用两组 NAND flash 片内交叉写入的命令地址和数据加载时间来填补烧写时间.最后用硬件方式在 FPGA中分别实现了上述各种写入控制方式的控制器.实验结果表明:本文实现的片内并行写入和片内交叉并行写入是普通写入方式速度的1.48903倍和3.27706倍,而本文提出的写入控制方法的写入速度是普通写入方式的3.96038倍,高于片外4级流水线的性能情况下,将 FPGA 管脚资源占用节省20%,有效降低了成本和记录系统实现难度.     

CORDIC-based FPGA hardware design method for biped walking gait

In this paper, a simple oscillator-based biped walking method is described and a CORDIC-based FPGA hardware design method is proposed to effectively generate a walking gait in a biped robot. Based on the simple oscillator-based model, some equations represented by sinusoidal functions are proposed to describe a biped walking as a complete walking process with three modes (starting mode, gait cycle mode, and ending mode) and six phases. In these six phases, these oscillation parameters can be represented by the swing length, the step length, and the lifting height of the biped robot. Then an FPGA hardware structure based on the CORDIC operator named circular rotation is proposed and implemented on an FPGA chip. Finally, some comparison of the proposed CORDIC-based FPGA hardware method and the software method are presented. We can see that the proposed hardware method significantly reduces the processing time to generate gait trajectories of a biped robot.     

基于复用模型的高速光电扫描仪性能的改进研究

提出了一种基于FPGA和DDRⅡ的JPEG图像压缩模式。在此基础上完成了A3高速光电扫描仪的设计与实现,解决了高速扫描仪中硬件资源与扫描速度相互制约的问题。通过内外存储器流水式复用模型,在降低片上RAM消耗的同时构建灵活、快速的大数据量存储与传输模式。采用高效的分时复用数据链路实现JPEG图像压缩,进一步提高硬件模块的压缩和传输速度。对采用中低端FPGA芯片设计的A3高速扫描仪的测量结果表明,在300 dpi分辨率下扫描A3幅面纸张的速度可达140面/min,扫描延时小于1 ms,压缩前后峰值信噪比高达86.9dB,完全满足高端高速扫描仪的要求。该模式的实现极大地降低了高端高速光电扫描仪对于硬件资源的要求,也可推广应用到其它幅面的高速光电扫描仪中。