Comparative analysis of wideband CMOS low-noise amplifiers for the RF range

A formalized method is presented for the circuit design of wideband low-noise amplifiers (LNAs) for RF applications. For a variety of LNAs thus obtained, a comparative performance analysis is performed by computer simulation in the frequency domain, involving optimization of small-signal LNA models. Optimal designs are thus identified showing a low reflection coefficient and a high gain over a wide frequency range extending to several gigahertz. Account is taken of limitations imposed by existing manufacturing technologies. For the sake of simplicity, the LNA configurations considered do not include frequency-selective networks.     

CMRR-bandwidth extension technique for CMOS differential amplifiers

An exemplary design demonstrates how to extend the Common-Mode-Rejection-Ratio (CMRR) bandwidth of a CMOS differential amplifier. The design presented uses MOSFETs with a channel length of 180 nm. A novel circuit technique is employed that partially compensates for the output capacitance of the tail current sink, thereby more than quadrupling the CMRR bandwidth in the example considered.     

An improved frequency compensation technique for CMOS operational amplifiers

The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.     

Low-noise room-temperature wideband parametric amplifiers

Two room-temperature parametric amplifiers are described which have gains of 26 dB. One has an excess noise temperature of between 74 and 85 K across the band 3.7?4.2 GHz, and the other has an excess noise temperature of between 85 and 99 K across the band 7.25?7.75 GHz.     

Biasing technique via bulk terminal for minimum supply CMOS amplifiers

A biasing technique for minimum supply CMOS amplifiers is proposed. The bulk terminals of the input transistors of a pseudo-differential amplifier are exploited in a switched-capacitor control loop to set the quiescent current. Simulations on a design powered with 0.7 V show that the performance obtained is comparable to that of a traditional differential pair supplied with 1 V.     

Low-noise wideband indium-phosphide transferred-electron amplifiers

X band pulsed, InP transferred-electron reflection amplifiers have been characterised by a study of the small-signal admittance, the large-signal dynamic conductance and the noise figure. These measurements have been made as functions of voltage, frequency and temperature on a number of different vapour epitaxial layers. The lowest observed noise figure was 8.8 dB at 10.0 GHz. An instantaneous bandwidth of more than 4 GHz at 7 dB gain has been obtained using a simple impedance-equalisation circuit.     

Dynamic CMOS amplifiers

The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase charge-carrying capacity. The chip size is 7.1 mm X 4.7 mm and 13 percent of the chip area is occupied by the CCD clock generator. The typical power dissipation is 205 mW in the active mode at 1 MHz and 40 mW in the standby mode at 50 kHz. Only 25 percent of the total power is devoted to the CCD clock generation at 1 MHz. The device is processed witlh an n-channel double level polysilicon-gate technology.     

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.     

Adaptive biasing CMOS amplifiers

Two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced. As a result, these amplifiers combine a very low standby power dissipation with a high driving capability. The first amplifier, suited for SC filters, is fairly small (0.075 mm/SUP 2/) and has a slew rate which is more than an order of magnitude better than micropower amplifiers presented earlier. The second amplifier can be used as a micropower buffer. Nearly the whole supply current is used to charge the load capacitor so that this amplifier has a high efficiency.     

New wideband microstrip antenna using log-periodic technique

A novel wideband microstrip antenna using a series-fed linear array of patch resonators in a log-periodic arrangement is described. A 9-element example gives good input v.s.w.r. and radiation control over a 30% bandwidth with better than 70% efficiency. The new array configuration gives wider bandwidth than single-layer or stacked microstrip patches combined with better efficiency than patches on lossy substrates or microstrip spirals.     

CMOS wideband analogue delay stage

A new second-order all-pass filter with maximum achievable delay-bandwidth-product (DBW) is presented. The proposed circuit will be used as a wideband delay element in impulse radio ultra-wideband transceivers. Benefiting from a simple architecture, the proposed circuit achieves a 60 ps delay across a 10 GHz bandwidth, which is the largest delay ever reported over such a wide bandwidth. In addition, the most noticeable advantage of this delay circuit is the small variation of group delay across a wide frequency range, which means negligibly small phase distortion introduced by the circuit     

Design techniques for high-frequency CMOS switched-capacitorfilters using non-op-amp-based unity-gain amplifiers

A fully differential non-op-amp-based unity-gain amplifier (UGA) is proposed, whose 3-dB frequency can be as high as 250 MHz in 3.5-μm p-well CMOS technology. The purpose is to develop a new design concept for high-frequency switched-capacitor (SC) filters which uses balanced non-op-amp type UGAs with tunable gain to replace conventional op-amp-based unity-gain buffers (UGBs). The proposed UGA has a normal gain of unit, but it has a greater bandwidth, better setting behavior, smaller chip area, and less transistors than op-amp-based UGB. The new UGA also has a fully differential balanced configuration. The balanced configuration and proper predistortion by CAD tools can reduce the error due to linear parasitic capacitances. Experimental results prove the capability of the proposed structures in the realization of high-frequency SC filters over the megahertz range     

On numerical design technique of wideband microwave amplifiers based on GaN small-signal device model

This work presents an application of Normalized Gain Function (NGF) method to the design of linear wideband microwave amplifiers based on small-signal model of a device. NGF has been originally developed to be used together with an S-parameter (*.s2p) file, whereas this work enables the NGF to be able to work with explicit S-parameter formulae derived from the small-signal model of the device. This approach provides the designer to be able to use simple set of S-parameter equations instead of S-parameter file of the device. Representation of the device simply by several model equations not only eliminates the need of carrying large number of data but also provides the capability of equation-based easy, realistic and equispaced S-parameter data generation in any desired resolution in frequency axis without requiring interpolation. NGF is defined as the ratio of T and |S₂₁|², i.e. T_N = T/|S₂₁|², gain function of the amplifier to be designed and transistor forward gain function, respectively. Synthesis of output/input matching networks (OMN/IMN) of the amplifier requires two target gain functions in terms of T_N, to be used in two sequential non-linear optimization procedures, respectively. An amplifier with a flat gain of ~10 dB operating in 0.8–2.35 GHz is designed using a small-signal model of an experimental GaN-HEMT. Theoretical amplifier performance obtained in Matlab is shown to be in excellent agreement with the simulated performance in MWO (Microwave Office, AWR Inc.). A prototype low-power amplifier having a ~10 to 12 dB gain, operating in (0.9–1.5 GHz) is also produced and measured which yielded good performance results.     

CMOS wideband auto-tuning phase shifter circuit

A novel auto-tuning phase shifter circuit suitable for integrated circuit implementation is presented. The circuit exhibits simple structure and provides phase shifting over three decades of frequency, 2 kHz-2 MHz, with a minimal phase error, less than 3.5%. Simulation results using 0.5 um CMOS technology and power supply plusmn2 V are included.     

Ultra low-voltage CMOS transconductance amplifiers

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail- to-rail input and output swing. The current headroom is 3???A and the supply voltage is 300?mV. For supply voltages down to 300?mV simulated data shows that the maximum clock frequency is approximately 600?MHz.     

Novel single-ended CMOS transconductance amplifiers

Two novel CMOS single-ended amplifiers are presented. Suitable for switched-capacitor-filter designs, they exhibit high gain and bandwidth as well as high PSRR, low power and small size.     

Design of CMOS amplifiers with offset rejection using positive-feedback QFG transistors

Two novel complementary design techniques of very-low DC gain CMOS amplifiers are presented. They are based on two classical positive-feedback structures for gain enhancement, increasing the equivalent load resistance and the transconductance of the input differential pair respectively. Quasi-Floating Gate transistors have been employed for designing frequency-dependent structures that reduce strongly the amplifier gain in DC and at very low frequencies, allowing the conventional high gain at frequencies starting at a few Hz. These broadband features make the proposed design techniques suitable for applications where weak input signals with large DC offset voltages have to be handled, such as biomedical signal processing or direct conversion communication receivers. Both ideas have been applied to simple one stage OTAs that have been fabricated in a 0.5 μm n-well technology. Measurement results are provided for validating the proposed techniques.     

Gigahertz-band high-gain GaAs monolithic amplifiers using parallelfeedback technique

A high-grain multistage amplifier design technique is described. As countermeasures against FET drawbacks, the drain conductance dispersion was modeled and the DC parallel feedback was applied against process variations. Based on these and further feedback techniques, a limiting amplifier and a gain-controllable amplifier for satellite communication systems were designed and fabricated utilizing an 0.8 μm gate-length ion-implanted GaAs MESFET process. Moreover, their packages were developed considering stability conditions. A 45 dB 0.1-3.5 GHz limiting amplifier and a 22-38 dB 0.1-2.5 GHz gain-controllable amplifier were developed     

铒铥共掺碲基质宽带光纤放大器研究

文章作者分析了铒铥共掺碲基质光纤放大器在980 nm泵浦下Er~(3+)-Tm~(3+)离子之间的能量转移过程,建立了速率方程和功率传输方程,并通过仿真得出了其放大增益随光纤长度和泵浦功率的变化规律.仿真结果表明:通过优化光纤长度和泵浦功率,该放大器可以在1 440～1 540 nm波段得到高达50 dB的平坦增益.     

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.