Localized relaxation theory of circuits and its applications in electro-thermal analyses

In the high-performance IC design with increasing design complexity,it is a very important design content to efficiently analyze IC parameters.Thus,the electro-thermal (ET) analyses including power/ground (P/G) analysis and thermal analysis are hot topics in today’s IC research.Since ET analysis equation has a sparse,positive definite and strictly diagonally dominant coefficient-matrix,we prove that the ET analysis has the advantage of locality.Owing to this advantage,localized relaxation method is formally proposed,which has the same accuracy as the global relaxation done with the constraint of the same truncation error limitation.Based on the localized relaxation theory,an efficient and practical localized successive over-relaxation algorithm (LSOR2) is introduced and applied to solve the following three ET analysis problems.(1) Single-node statistical voltage analysis for over-IR-drop nodes in P/G networks;(2) single-node statistical temperature analysis for hot spots in 3D thermal analysis;(3) fast single open-defect analysis for P/G networks.A large amount of experimental data demonstrates that compared with the global successive over-relaxation (SOR) algorithm,LSOR2 can speed up 1-2 orders of magnitudes with the same accuracy in ET analyses.     

局部松弛电路理论及其在电热分析中的应用

在复杂度日益增高的高性能集成电路设计中,高效的性能分析是一项重要的设计内容,其中由电源线/地线网络(P/G)分析与芯片热分析构成的电热分析则是目前研究的热点问题.针对电热分析方程所具有的大规模稀疏(电导或热导)系数矩阵,根据该系数矩阵所具有的对称正定严格对角占优等特性,本文从理论上证明了电热分析具有局部性,在相同的截断误差限松弛结束条件下,局部松弛和全局松弛具有相同的松弛精度.基于局部松弛理论,本文提出了一个高效实用的局部过松弛(SOR)算法(LSOR2),并在文章最后将其用于如下的3个具体的电热分析问题研究:(1)P/G网中的过压降点电压变化统计分析;(2)3D热分析中的过热点温度变化统计分析;(3)单开路故障下的P/G网快速分析.实验数据表明:与全局SOR算法相比,在保证精度的前提下,LSOR2算法可以将电热分析的求解速度提高1-2个数量级.     

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y toπtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.     

电热分析研究的现状与展望

随着IC工艺进入纳米工艺时代,集成度与工作频率的增加,伴随性能提高的是不断增加的芯片功耗.高功耗的直接后果是产生了高供电电流和高功耗密度,而过大的供电电流降低了供电网络的供电电压;过大的功耗密度升高了内核温度,反过来又会增加电路时延,降低芯片的性能.所以在芯片设计中,必须对芯片功耗、供电网络、3D热分析进行快速而精确的电热分析;同时,漏电流功耗随工作温度升高而明显增加所造成的电热耦合效应,以及纳米工艺所带来的较大工艺参数变化,都提高了电热分析的难度.文中给出了电热参量(功耗、供电电压和内核温度)分析的重要性与研究现状,展望了纳米工艺下日益显著的工艺参数变化对电热分析所带来的挑战.     

A model for synchronous switching circuits and its theory of correctness

Following Bryant [2], an algorithm is given for translating a switching circuit design into a program that simulates its dynamic behavior. A theory of assertions based on Dijkstra [5] and UNITY [4] is then developed to formalize specifications of hardware circuit designs and to establish their correctness. Both combinational and sequential circuits are taken into account both in N-mos and C-mos; the latter turns out to be much simpler.Chaochen Zhou in on leave from the Software Institute, Academia Sinica     

Simulation of large nonlinear circuits

This paper discusses some of the techniques currently being researched to resolve the problem of time-domain simulation of large nonlinear systems such as those that may be realized on VLSI circuits.     

High power GaN‐HEMT SPDT switches for microwave applications

In this article, the design, fabrication, and on‐wafer test of X‐Band and 2–18 GHz wideband high‐power SPDT MMIC switches in AlGaN/GaN technology are presented. The switches have demonstrated state‐of‐the‐art performance and RF fabrication yield better than 65%. Linear and power measurements for different control voltages have been reported and an explanation of the dependence of the power performances on the control voltage is given. In particular, the X‐band switch exhibits a 0.4 dB compression level at 10 GHz when driven by a 38 dBm input signal. The wideband switch shows a compression level of 1 dB at an input drive higher than 38 dBm across the entire bandwidth. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

随机行走算法研究及其在电源/地线网络瞬态优化中的应用

实验分析了电源/地线(P/G)网络的随机行走算法,与传统的预优共轭梯度法比较发现,当随机行走求解较少节点时性能较好,但在大规模P/G网络瞬态分析中相对较慢.通过修改随机行走过程进行伴随网络的瞬态分析,提出一种快速计算灵敏度的算法.实验结果表明,该算法计算时间较短,与精确结果误差较小.     

SRT除法器及其算法的研究

给出了一种新型的SRT除法器的实现,对其实现的构架和相应算法的实现过程进行了全面的描述.这种新的除法器算法在保持精度的条件下使用较小的资源;可以实现8位、16位、32位等更高位的除法运算,提高运算速度,较其它算法有更快和位数可调的优点.     

利于GPU计算具有线性并行度的P/G网SOR求解算法

近年来电子设计自动化(EDA)研究人员尝试利用图形处理器(graphic processing unit,GPU)提供的高性能计算能力对IC参数分析进行加速研究.为了利用GPU进行电源线/地线网络(power/ground network,P/G网)快速分析,设计了一种基于经典的连续过松弛(successive over-relaxation,SOR)算法的高效P/G网分析并行算法.基于GPU并行计算加速原理,此算法进行了如下改进:1)采用红-黑次序的松弛策略.将所有的节点分为红黑两类,红色节点的所有邻点只有黑色节点、黑色节点的所有邻点只有红色节点,红色节点与黑色节点交替松弛,保证了GPU并行计算中的数据一致性.对于具有N个节点的P/G网而言,一次红色节点或黑色节点松弛可以同时对N/2个节点进行松弛操作,即理论上可以同时启动N/2个并行线程.2)优化数据结构.实现了对数据空间的合并访问,以保证对GPU全局存储空间的最优访问.3)在共享存储器内通过并行归约对松弛标记进行快速统计,同时利用zero-copy技术进行松弛标记的快速拷贝,以快速决定是否继续松弛.大量的实验结果表明:与单线程的CPU程序相比,此算法的加速倍数随GPU所提供物理线程的数目增加而线性增加,可以获得最大242倍的加速效果,是目前EDA研究领域中加速效果最好的GPU算法.     

人工免疫系统的基本理论及其应用

介绍了生物免疫系统的工作机制与特性及人工免疫算法,且将人工免疫系统与其他智能方法进行比较.还归纳了人工免疫系统的工程应用并对人工免疫系统需深入研究的方向进行了展望.     

The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications

The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6-10 times faster without significant loss in accur     

一种基于BP神经网络的集成电路PHM模型

提出了一种基于数据驱动的集成电路故障预测与健康管理(PHM)模型,该模型基于反向传播(BP)神经网络算法,避免了对集成电路老化失效物理机理的依赖,能有效拟合集成电路失效的非线性函数关系。以已编程应用设计的FPGA为目标器件,通过实验提取参数样本进行模型训练,并将模型应用于实测验证。结果表明,该模型输出结果与实测结果吻合良好,能有效满足集成电路故障预测与健康管理的实际应用。     

555定时电路的原理及应用

555定时器是一种常用的双极型中规模集成电路,用它能够方便简单的实现定时、波形变换、自动报警。本文从元件结构、工作原理和典型工作模式三个方面介绍了555定时电路的使用方法。     

基于压缩式双共轭梯度算法对大规模电源/地线网络的快速分析

采用压缩式双共轭梯度算法分析大规模电源/地线网络.首先以稀疏存储结构对大规模的系数矩阵进行压缩处理,然后采用双共轭梯度算法对网络进行模拟.双共轭梯度算法采用2组共轭向量组作为搜索方向,收敛速度快.实验数据表明:在保证精度的情况下,该算法在加快电路网络分析求解效率的同时,大幅度地节省了计算所占用的内存,它适用于分析超大规模的电源/地线网络.     

一种大规模模拟电路快速故障诊断新方法

针对传统大规模模拟电路故障诊断方法在多故障条件下的故障定位过程复杂、测前工作量大等问题, 提出了一种新的故障诊断方法——成组撕裂法。将大规模模拟电路按照拓扑特性和成组撕裂准则进行撕裂, 得到低维度的故障特征向量; 基于模式识别思想, 选用具有高度并行分类能力的神经网络作为分类器, 隐含层传递激发函数选择具有快速收敛特性的小波函数。经仿真验证该方法能实现故障特征向量的快速分类并得出故障诊断结果。与目前已有的互校验（multiple-test-condition, MTC）和交叉撕裂搜索法相比, 该方法有测前工作量小、诊断次数和计算量少、对多故障检测能力和工程实践性强等特点。     

GNet: A generalized network model and its applications in qualitative spatial reasoning

A data model, named generalized network (GNet), is proposed to perform various network-tracing tasks, especially tracing conceptual proposition networks in qualitative spatial reasoning (QSR). The GNet model can be defined as a 6-tuple: (V, A, q, ⊕, ∼, L). By specifying each element in the 6-tuple, a GNet can function as a conventional network, or an activity on edge (AOE) network, etc. The algorithm for searching for the generalized optimum path weight (GOPW) between two vertices in a GNet is developed by extending the Bellman-Ford algorithm (EBFA). Based on the GNet model, this paper focuses on representing spatial knowledge, which consists of a set of binary relations. We present two applications of GNets, namely the RCC8 network and the hybrid RCC8 network involving cardinal direction relations. Both can be traced to infer new spatial knowledge using EBFA. The applications demonstrate that the GNet model provides a promising approach to dealing with proposition-based geospatial knowledge based on weak composition. We also point out that EBFA can check whether a network is algebraically closed, or path-consistent when the corresponding composition table is extensional.     

Recent advances in theory and applications of substrate‐integrated waveguides: A review

The use of substrate integrated waveguides (SIW) for microwave and millimeter wave integrated components has increased dramatically over the last decade. They mimic the performance of conventional metallic waveguides and they are fabricated using printed circuit boards using the top and bottom metallization with two rows of vias forming the side walls. This creates a low profile, compact, and light weight alternative to conventional metallic waveguides, and they allow a direct interconnection with printed circuit boards and active components. This article reviews the fundamental theory, documents the research that has been performed over the past decade, and summarizes progress up to the recent state‐of‐the‐art including novel SIW structures for passive circuits and antennas as well as new applications for reconfigurable and printed circuits using SIW technology. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:129–145, 2016.     

基于虚拟仪器文氏桥混沌电路的建模与仿真

为缩短混沌电路的研究周期,提出了一种利用虚拟仪器实现混沌电路的方法。采用改进型欧拉算法对文氏桥混沌电路的状态方程进行近似处理,建立了相应的离散模型。在虚拟仪器(Labview)环境下进行数值仿真,可观察到在电路参数变化时电路动力学行为的演变过程,并通过构建采集系统,实现了文氏桥混沌电路离散模型的混沌信号输出。仿真结果与已有研究结果完全一致,有效地体现了"软件既是仪器"的概念。     

Input-dependent neural network trained by real-coded genetic algorithm and its industrial applications

This paper presents an input-dependent neural network (IDNN) with variable parameters. The parameters of the neurons in the hidden nodes adapt to changes of the input environment, so that different test input sets separately distributed in a large domain can be tackled after training. Effectively, there are different individual neural networks for different sets of inputs. The proposed network exhibits a better learning and generalization ability than the traditional one. An improved real-coded genetic algorithm (RCGA) Ling and Leung (Soft Comput 11(1):7–31, 2007) is proposed to train the network parameters. Industrial applications on short-term load forecasting and hand-written graffiti recognition will be presented to verify and illustrate the improvement.