On the RF Series Resistance Extraction of Nanoscale MOSFETs

A new extraction method of series resistance based on the radio frequency S-parameter measurement for sub -0.1 mum metal oxide semiconductor field-effect transistor is presented. The practical limit of conventional methods is analyzed from measurement and simulation. From this analysis, analytical expressions are derived, and linear regression techniques are used to extract the series resistances. The proposed method improves the accuracy and reduces the measurement frequency.     

基于粒子群优化算法的BSIM SOI模型参数提取

本文给出一种基于粒子群优化算法的BSIM SOI MOSFETs模型参数提取方法.该方法采用全局优化策略,计算简单,对初值依赖性低,使用浮点数编码方法,避免了数码转换时所出现的误差.与遗传算法参数提取相比,粒子群优化算法无需进行交叉、变异等操作,容易理解,易于实现,且收敛速度更快.对用该方法得到的参数值代入器件模型进行了计算,计算结果与测试结果吻合很好.本方法亦可用作对其他种类的MOSFETs进行全局参数提取.     

Effects of gate structures on the RF performance in PD SOI MOSFETs

The radio-frequency (RF) performance of PD silicon-on-insulator metal oxide semiconductor field effect transistors with T-gate and H-gate structures has been investigated. Our measurement shows that H-gate devices have larger cutoff frequency and smaller minimum noise figure than T-gate devices. This improved RF performance in H-gate devices can be explained mainly by the enhancement of transconductance resulting from the gate extension induced inversion charges and the low gate resistance. We conclude that the H-gate structure is superior to the T-gate structure for the design of the low-noise amplifier (LNA).     

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

On the body-source built-in potential lowering of SOI MOSFETs

This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-insulator (SOI) MOSFETs. Based on body-source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.     

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.     

Extraction of substrate parameters for RF MOSFETs based on four-port measurement

In this work, a new method for extracting substrate parameters of radio frequency (RF) metal oxide semiconductor field effect transistors (MOSFETs) based on four-port measurement is presented. A T-liked substrate resistance network is used and the values of all components in the cold MOSFETs were extracted directly from the four-port data between 250 MHz and 8.5 GHz. The output admittance Y/sub 22/ can be well modeled up to 26.5 GHz based on the extracted substrate resistances and the other extrinsic capacitances extracted from an active device.     

Evaluation of RF Capacitance Extraction for Ultrathin Ultraleaky SOI MOS Devices

This letter evaluates a radio-frequency (RF) method to extract the gate capacitance for SOI MOSFETs with ultrathin ultraleaky gate dielectrics. Conventional methods such as two-element and three-element methods using precision impedance analyzer were also compared. The RF method scans the RF capacitance data, assesses its lower and upper limits, and extracts the SOI gate capacitance accurately independent of gate oxide thickness     

Comparison of hot carrier-induced RF performance degradation in H-gate and T-gate SOI MOSFETs

The RF performance degradation of silicon-on-insulator (SOI) MOSFETs with H-gate and T-gate structures after hot carrier stressing has been investigated. Our experimental results show that the RF performance degradation is more significant than the dc performance degradation after hot carrier stressing. Also, the degradation of the H-gate device is more significant than that of the T-gate device due to the higher drain current. Since the degradation of minimum noise figure is the most significant, the hot carrier effects should be taken into account in the design of LNA using the H-gate device although its RF performance is better than that of the T-gate device.     

射频MOSFET噪声模型研究

对0.13μm MOSFET噪声建模和参数提取技术进行了研究,在精确地提取了小信号模型参数之后,利用噪声相关矩阵技术从测量的散射参数和射频噪声参数直接提取了栅极感应噪声电流■、沟道噪声电流■和它们的相关系数,并用PRC模型中的参数来表示。将参数提取结果带入ADS中进行仿真,在2～8GHz频段上仿真结果与测量数据吻合良好。     

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage     

Short-channel effects in SOI MOSFETs

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed     

On the high-frequency characteristics of substrate resistance in RF MOSFETs

The high-frequency (HF) behavior of substrate components in MOSFETs is studied at different bias conditions for a 0.35 /spl mu/m BICMOS technology in the frequency range up to 10 GHz. It was found that the observed strong bias dependence of the real part of admittance y/sub 22/, Re{y/sub 22/}, is mainly contributed by the channel conductance. A very weak bias dependence of substrate resistance was found after deembedding the measured y/sub 22/ to remove the influence of channel resistance R/sub ds/ and gate-to-drain capacitance C/sub gd/. The results are key to the understanding and modeling of the HF behavior of MOSFET substrate components for RF IC design.     

On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

An analytical total gate capacitance C/sub G/ model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. The model accounts for the effects of carrier-energy quantization and inversion-layer screening and is verified via self-consistent numerical solutions of the Poisson and Schro/spl uml/dinger equations. Results provide good physical insight regarding C/sub G/ degradation due to quantization and screening governed by device structure and/or transverse electric field for nanoscale DG and FD/SOI MOSFETs. Two limits of C/sub G/ at ON-state are then derived when the silicon film t/sub Si/ approaches zero and infinity. The effect of inversion-layer screening on C/sub G/, which is significant for ultrathin Si-film DG MOSFETs, is quantitatively defined for the first time. The insightful results show that the two-dimensional screening length for DG MOSFETs is independent of the doping density and much shorter than the bulk Debye length as a result of strong structural confinement.     

Linear dynamic self-heating in SOI MOSFETs

A model for small-signal dynamic self-heating is derived for the general case of a two-port device and then specialized to the case of an SOI MOSFET. The model is fitted to measured data for an SOI MOSFET and shown to accurately describe the frequency dependence of the self-heating. For this device, three time constants of 0.25 μs, 17 ns, and 90 ps adequately characterize the thermal response, showing that self-heating effects are active over a very wide frequency range     

Subthreshold slope in thin-film SOI MOSFETs

The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given     

Quantum-mechanical effects in trigate SOI MOSFETs

A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands