Investigation of temperature-dependent small-signal performances of TB SOI MOSFETs

This paper investigated the temperature dependence of the cryogenic small-signal ac performances of multi-finger partially depleted (PD) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs), with T-gate body contact (TB) structure. The measurement results show that the cut-off frequency increases from 78 GHz at 300 K to 120 GHz at 77 K and the maximum oscillation frequency increases from 54 GHz at 300 K to 80 GHz at 77 K, and these are mainly due to the effect of negative temperature dependence of threshold voltage and transconductance. By using a simple equivalent circuit model, the temperature-dependent small-signal parameters are discussed in detail. The understanding of cryogenic small-signal performance is beneficial to develop the PD SOI MOSFETs integrated circuits for ultra-low temperature applications.     

Compact modeling of a PD SOI MESFET for wide temperature designs

A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of −180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.     

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.     

MOSFET modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction.     

A New Approach for SOI Devices Small-Signal Parameters Extraction

SOI devices are frequently used nowadays in the RF and HF field. Design of complex SOI integrated circuits involves a prior detailed analog simulation, that can only be performed through accurate SOI active components models. We are interested here in linear operation modeling; we test new methods for small-signal parameters determination, suitable for a conventional MOSFET high-frequency model and somewhat inspired from methods applied to MESFET technology. In this paper, we deal mainly with extrinsic parameters, for which we obtain reliable estimation on a large frequency range. Our finally adopted extraction procedure takes closely into account the model topology, which reflects the device electrical behavior. We completely describe the procedure, from measurements to the extracted equivalent circuit simulation, without having to optimize parameters and with a straightforward extrinsic elements extraction.     

Deep submicron PDSOI thermal resistance extraction

Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

A physically based compact model of partially depleted SOI MOSFETsfor analog circuit simulation

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates     

Analysis of high speed p-i-n photodiode S-parameters by a novel small-signal equivalent circuit model

A novel small-signal radio frequency (RF) equivalent-circuit of the side-illuminated input tapered waveguide-integrated p-i-n photodiodes (WG PIN PD) is proposed. The proposed RF equivalent-circuit involves both the carrier-transit effect and the external resistance-capacitance (RC) time constant limitation on the frequency response of the p-i-n PD. The carrier-transit effect is realized by adding an RC circuit to an ideal voltage-controlled current source as the input opto-RF equivalent circuit. The carrier transit-time effect is equivalently represented by the time-constant of this input RC circuit. This new equivalent circuit model fits well with both the measured reflection and optoelectronic conversion parameters of the WG PIN PD in a broad frequency range from 45 MHz to 50 GHz.     

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

CMOS for the mixed-mode applications has gained much interest recently. While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling guidelines for improving the analog performance of silicon-on-insulator (SOI) MOSFETs. This paper presents a systematic and quantitative comparison between the analog characteristics of the bulk and SOI technology. The intrinsic gain, f/sub T/ and g/sub m//I/sub ds/ ratio are considered as a metric for this comparison. It is shown that, even for the operating frequencies in the range of gigahertz (where the ac kink effect is suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to the capacitive drain-to-body coupling. Based on our study, we show that hat the gate-workfunction engineering (close to mid-gap workfunction) is essential in fully depleted SOI (FDSOI) devices for improving analog performance. The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. An increased gate control in double-gate MOSFETs can provide very high output resistance for short-channel devices.     

Deep-submicrometer DC-to-RF SOI MOSFET macro-model

We present a submicrometer RF fully depleted SOI MOSFET macro-model based on a complete extrinsic small-signal equivalent circuit and an improved CAD model for the intrinsic device. The delay propagation effects in the channel are modeled by splitting the intrinsic transistor into a series of shorter transistors, for each of which a quasistatic device model can be used. Since the intrinsic device model is charge-based, our RF SOI MOSFET model can be used in both small and large-signal analyses. The model has been validated for frequencies up to 40 GHz and effective channel lengths down to 0.16 μm     

全耗尽SOIMOSFET辐照导致的阈值电压漂移模型

报道了全耗尽SOI MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的加固SOI器件与电路的模拟.讨论了抑制阈值电压漂移的方法.结果表明,对于全耗尽SOI加固工艺,辐照导致的埋氧层(BOX)氧化物电荷对前栅的耦合是影响前栅阈值电压漂移的主要因素,但减薄埋氧层厚度并不能明显提高SOI MOSFET的抗辐照性能.     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

Extraction of substrate parameters for RF MOSFETs based on four-port measurement

In this work, a new method for extracting substrate parameters of radio frequency (RF) metal oxide semiconductor field effect transistors (MOSFETs) based on four-port measurement is presented. A T-liked substrate resistance network is used and the values of all components in the cold MOSFETs were extracted directly from the four-port data between 250 MHz and 8.5 GHz. The output admittance Y/sub 22/ can be well modeled up to 26.5 GHz based on the extracted substrate resistances and the other extrinsic capacitances extracted from an active device.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.