Vertex cutsets and circuit layout

The distribution of the equipment elements of an electrical circuit in groups corresponding to units is reduced to finding a minimum vertex cutset of an undirected graph derived from the circuit.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

Simulation approach for achieving layout independent polysilicongate etching

Profile and dimension control mechanism in polysilicon gate etching is studied systematically by the use of two-dimensional (2-D) etching topography simulator. Reaction rates are calculated by taking into account interactions between incoming ion/radical fluxes and an ever-changing macroscopic adsorbed particle layer on the film surface. A qualitative guideline is presented for achieving both anisotropic etched-profile formation and the dimension difference minimization between the inner line pattern width w_i and the outermost line pattern width w_e in repeated line and space configuration. When w_c>w_i>w_m (resist mask width), following two possible measures are necessary. One is to make gas pumping speed large for shortening the residence time of depositive radicals. The other is to make cathode temperature high for lowering sticking coefficient of depositive radicals. These are effective in reducing the amount of deposited film especially at the sidewall of external part of the outermost line pattern (SEP). Higher gas pressure is also effective in sputtering the deposited film especially at SEP     

IC卡读写器天线电路设计

非接触式IC卡读写器作为新兴事物具有广泛的应用前景,作为中间部件的天线起着连接两端数据源的重要作用。首先分析天线电路的原理与结构,然后给出并比较天线匹配电路设计的两种方法:并联分流式与串联分压式,研究如何确定关键元件的取值,最后通过实例进行仿真分析。计算与仿真结果表明,采用并联分流式的匹配电路设计的天线具有较好的电磁耦合效率,自行研发的读写器使用该种方案,并取得良好效果。     

Fractal circuit layout for spatial decorrelation of images

Peano-Hilbert curves can be used to destroy the spatial autocorrelation of an image. The effectiveness of the approach, which applies to cryptography and associative memories, stems from the fractal structure of such curves. The fractal topology supports pseudo-random pixel remapping, and the self-similarity of the layout strongly simplifies electronic circuit implementations     

Maximizing pin alignment in semi-custom chip circuit layout

We consider the problem of logically permuting pins of a semi-custom chip circuit layout in order to maximize the number of connections that can be realized in the polysilicon layer. As the problem is NP-hard, we present an infinite hierarchy of heuristics, including an algorithm which produces an optimal solution. The heuristics can be tuned to yield approximate solutions of varying degree, as well as an optimal solution. The tradeoff lies in the length of runtime. We have implemented the procedures and demonstrate their behavior with one real and various randomly generated examples.     

基于进化的电路自动设计方法

电路进化设计是可进化硬件(Evolvable:HardWare，简称EHW）研究的重要内容，即利用进化计算技术配置电路的内部结构以获得所需的电路功能。该方法的优点包括：可获得常规设计方法考虑范围以外的最佳设计；不依赖于先验知识，但仍可利用巳有的知识和经济来提高设计的频率；自动化程度高，便于实施：因此有希望替代常规设计方法，实现复杂和大规模电路的自动设计。本文简述EHW的基本概念，介绍电路进化设计的基本原理、关键技术和主要进展，讨论重要的开放问题及未来的研究方向。     

全球化是集成电路卡发展的主要趋势

介绍了多种集成电路卡的应用及发展。     

Performance-driven circuit and layout co-optimization for deep-submicron analog circuits

The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

基于V-I曲线的电路板故障测试卡的实现

设计了一种基于V-I曲线的电路板故障测试卡。它采用PCI接口的形式,在上位机的控制下产生测试所需的电压扫描信号,同时逐点采集其电流值,并实时将电压与对应的电流值经PCI接口送上位机做故障分析。该测试卡架构灵活,采用PCI卡＋专用测试诊断软件的模式,可用于各种类型电路板的故障测试,同时可扩展到分机及任意电气特性节点,特别适合现场及野外维修等场合。本文详细介绍了测试卡的硬件设计,包括原理图及关键程序段,最后设计了一个简单的测试DEMO,验证了预期的结果。     

社保卡和盒融卡结合面临的挑战

本文通过比较发卡主体的不同,指出了：社保卡与哪一家银行的金融卡结合是难以合理解决的问题。通过对金融卡的进一步分析,指出了：在目前的模式下发放金融IC卡,会重演磁条卡的无序竞争局面,难以为客户提供差异化的、有吸引力的服务。通过引入新的智能卡COS技术,采用以发卡人为中心的发卡模式,借助于互联网和PKI技术,金融IC卡的功能可以体现为一个智能IC卡应用,由用户（持卡人）决定是否下载使用。本文还进一步描绘了智能IC卡在互联网领域的应用前景。指出了智能IC卡可以作为“网络身份证”,为网络实名制提供有效的技术手段。     

Automated bias control (ABC) circuit for high-performance VLSIs

A biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSIs is described. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing the excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stages of signal amplification. Since feedback control of the ABC circuit ensures correct DC biasing even under large process deviations and circuit condition changes, a wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-μm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

一种抑制ESD保护电路闩锁效应的版图研究

针对具有低压触发特性的静电放电(electrostatic discharge,ESD)保护电路易闩锁的不足,本文结合CSMC0.6μm CMOS工艺,设计了一种可应用于ESD保护电路中的独立双阱隔离布局方案,这种方案不仅可以有效的阻断形成闩锁的CMOS器件固有纵向PNP与横向NPN晶体管的耦合,且兼容原有工艺而不增加版图面积。将此布局方案与常规保护环结构同时应用于笔者研制的具有低压快速触发特性双通路ESD保护电路中,通过流片及测试对比表明,该布局方案在不影响保护电路特性的同时,较常规保护环结构更为有效的克服了保护电路的闩锁效应,从而进一步提升了该保护电路的鲁棒性指标。本文的布局方案为次亚微米MOS ESD保护电路版图设计提供了一种新的参考依据。     

等离子对刚挠结合印制板用材料蚀刻的均匀性及其机理研究

等离子清洗是刚挠结合板去钻污的最重要的一个过程,它影响着镀铜与孔壁表面之间的结合力。获得平整、均匀的表面是金属化孔可靠性的重要保证。本文将从等离子机的腔体空间的均匀性、等离子机蚀刻时间的均匀性等研究着手,为等离子蚀刻均匀性研究提供可靠的实验环境。通过等离子蚀刻刚挠结合板不同材料的实验,并利用均匀设计的方法获得刚挠结合板用聚酰亚胺、丙烯酸胶及环氧树脂等不同材料的蚀刻速率与等离子蚀刻参数之间的非线性拟合关系。最后再根据方程进行讨论,获得刚挠结合板用材料蚀刻均匀性的参数。根据实验中,实验分析中出现的各种现象,本文等离子蚀刻提出最合理的机理解释,并使用该机理定性纠正非线性拟合方程中的拟合偏差。     

Multiple assignment of component types to feeder slots on automatedprinted circuit card placement machines

This paper investigates the benefits of allowing specific component types to be assigned to more than one feeder location on a printed circuit card automated placement machine. Until this experimental work, no known study has ever reported the relative improvement in cycle time when multiple assignment of component types is allowed. An experiment was designed to find the card specifications and machine operational characteristics under which the benefits of multiple assignment would be most advantageous. An integer programming heuristic was used to solve industry representative data sets for a variety of operational characteristics. For these data, it was found that multiple assignment of component types could reduce cycle time. Over all operational scenarios considered, an approximate 8% reduction in cycle time could be realized by allowing multiple assignment of component types versus not allowing multiple assignment. For those operational scenarios found to be most benefited by multiple assignment, such as card type families with a high coefficient of component variation, allowing multiple assignment across machines showed reduction of the cycle time by approximately 15% versus the alternative where no multiple assignment is allowed     

Automated hierarchical CMOS analog circuit stack generation withintramodule connectivity and matching considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples