一种时间交织ADC采样时间误差校正方法

提出了一种用于时间交织模数转换器(TIADC)通道间采样时间误差的校正算法。该算法是基于参考通道的后台校正算法。通过比较参考通道与带校准通道的输出差异提取出采样误差信息,并通过负反馈逻辑进行校准。该算法的校正模块硬件消耗低,可支持包括完全随机输入信号的多种类型输入信号。将该校正算法应用于一个4 GHz、8 bit四通道TIADC,后仿真结果表明,当输入信号接近奈奎斯特频率、存在其他非理想因素的条件下,该算法能将通道间采样时间误差相关的频谱尖峰抑制到35 dB。     

12位200MS/s交织A/D转换器设计

介绍了一个面向3G/4G LTE通信及雷达等应用的12位200 MS/s的高速低功耗A/D转换器(ADC).采用交织运放共享技术,可节省功耗,同时减小不同通道之间的增益失配、失调失配和带宽失配,提高ADC的性能.为了提高ADC的高频性能并避免时钟采样偏差带来的两路通道失配问题,采用一个工作在200 MS/s采样频率的统一的采样保持电路.芯片采用HJTC0.18 μm 1P6M CMOS的工艺制造,核心电路面积为1.6×4 (mm2),电源电压2.0V.流片测试结果表明,在4.9 MHz的输入频率下,无杂散动态范围(SFDR)为83.1 dB,信号噪声失真比(SNDR)为59.6 dB,模拟核心电流为120mA,FOM1和FOM2值仅为0.08 pJ/step和1.25 pJ/step.     

基于频域特性的时间交替模数转换系统采样时间误差校正算法

时间交替模数转换器(Time-Interleaved ADC,TIADC)通道间的采样时间相对误差严重影响了系统的无杂散动态范围(Spurious-Free Dynamic Range,SFDR).为校正采样时间相对误差,本文基于TIADC输出与模拟输入信号之间的频域关系,提出一种通过消除输出信号中的误差来校准TIADC的算法.该算法在对输出信号频率表达式进行泰勒近似的基础上构建理想输出信号,并采用最小均方差(LMS)算法来估算时间误差,旨在降低硬件设计的复杂度,提高误差校正的精确度.仿真和验证结果表明该校正算法很容易扩展到多通道,并且可以将输出频谱的SFDR提高约47dB.     

一种用于ADC采样的高精度时钟占空比校正方法

本文提出一种高精度时钟信号占空比校正方法,采用环路负反馈的理论产生延时控制电压,并通过延时可控的占空比调整电路来产生高精度占空比的时钟信号。基于0.18μm工艺对所提出的校正方法进行了具体电路设计和PVT全面仿真验证,输入频率在100MHz占空比变化范围6%~97%时,该方法都可以动态精确的输出频率为100MHz占空比为50%的信号,最大误差小于0.28%,功耗仅为4.8mW,为高精度ADC采样和转换提供了高效的解决方案。     

一种具有84.8dB SFDR和72dB SNDR的14位80MS/s CMOS模数转换器

本文描述了一种基于0.35μm CMOS工艺的14位采样率80MS/s的流水线型模数转换器的设计. 所提出的电荷分享校正技术消除了与信号相关的电荷注入效应, 加上片内的低抖动时钟电路, 保证了模数转换器的高动态性能. 一种信号电容开关技术和高对称版图减小了电容失配, 确保了模数转换器的总线性度. 测试结果表明, 该模数转换器在36.7MHz输入频率下, 实现了11.6位的有效位, 84.8dB的无杂散动态范围(SFDR), 72dB的信号噪声失真比(SNDR), 在无校准情况下获得了＋0.63/－0.6 LSB的微分非线性和＋1.3/－0.9 LSB的积分非线性. 输入频率200MHz时,仍然可以保持75dB的SFDR和59dB的SNDR.     

12 bit 200 MS/s时间交织流水线A/D转换器的设计

介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC).流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择.采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗.同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路.采用SMIC 0.13 μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm.测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 dB,信噪失真比(SNDR)为55.7 dB,ADC的品质因子(FoM)为1.07 pJ/conv.,而功耗为107 mW.     

一种12位25 MS/s采样保持电路设计

在流水线结构的A／D转换电路中,采样保持电路是整个电路的核心模块。同时采样保持电路通常是整个电路中功耗最大的模块,其性能直接决定了整个A／D转换器的性能。文章介绍了一种12位25MS／s采样保持电路。该采样保持电路采用SMIC0.25μm标准数字CMOS工艺进行设计。基于BSIM3V3Spice模型,采用Hspice对整个电路进行仿真。仿真的结果表明,电路在工作于25MS／s、输入信号频率为2．56MHz时,输出信号的SFDR为75．6dB,而整个电路的功耗仅为10．41mW。     

时间交织流水线ADC的双采样保持电路设计

基于SMIC0.18μm,1.8V工艺,设计了一种新型的双采样保持电路,可用于12bit、100MHz采样频率的时间交织流水线(Pipelined)ADC中.设计了一种采用了增益增强技术并带有一种改进的开关电容共模反馈电路的全差分运放.并且针对该双采样保持电路设计了特定的时钟发生电路.在cadence电路设计平台中利用Spectre仿真,结果表明:该采样保持电路可以实现12位、100MS/s采样速率和15mW功耗,满足系统设计要求.     

一个嵌入式应用的8位300MS/s折叠内插模数转换器

本文设计了一个1.4V电源电压8位300MS/s折叠内插结构的模数转换器。该模数转换器利用0.13μm CMOS工艺实现,有效面积仅为0.6mm2,非常适合嵌入式应用。系统对低功耗进行了优化。流水线式采样开关节省了用于实现信号完整建立而增加的额外功耗。失调平均电阻阵列被置于两级折叠电路之间也是出于节省功耗的考虑。该转换器在1MHz下达到了43.4dB的信噪失真比和53.3dB的无杂散动态范围,在奈奎斯特频率输入情况下信噪失真比和无杂散动态范围分别为42.1dB和49.5dB。测试结果表明在1.4V电源250MHz采样率下功耗为34mW,FoM值为1.14pJ/转换步长。     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

一个适用于多通道时间交织模数转换器采样时间误差校准算法的数模转换器

A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs’ skews by adjusting the boosted voltage.A similar bridged capacitors’ charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch’s demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.     

一种不带校正SFDR为85.2dB的14位100兆流水线模数转换器

This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.     

采用后台数字校准的12位100MHz流水线模数转换器

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.     

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3×1.6 mm~2, and consumes 205 mW at 1.8 V.     

一种基于数字后台校准技术的14 bit 500 MS/s 数模转换器

Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique

This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8×1.4 mm² in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200 MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4 MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49 dB–70.71 dB while consuming of 112 mW at a supply voltage of 1.1 V.     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...     

基于无采样保持和运放共享的10-bit 50-MS/s亚采样流水线模数转换器

摘要：本文采用提出的面积和功耗优化结构,设计了一个10-bit 50-MS/s的流水线模数转换器。本设计将采样保持和第一级转换电路融合为一个模块,既省去了前端采样保持电路,又避免了第一级中余差放大电路和子模数转换器延时路径需要匹配的问题,该模块具有功耗低稳定性高的特点。为了进一步降低面积和功耗,相邻两级间采用运放共享结构,该结构具有运放失调电压和级间串扰影响小的特点。该10-bit模数转换器的实现仅采用了四个运放。测试结果表明,当采样率为50MHz、输入为奈奎斯特频率时,获得52.67dB SFDR和59.44dB SNDR。当输入频率上升到两倍奈奎斯特频率时,该模数转换器仍然保持了稳定的动态性能。本设计采用0.35μm CMOS工艺实现,芯片有效面积仅为1.81mm2,50MHz采样率3.3V供电时功耗为133mW。     

一种有效位为11.3比特的14位100兆CMOS流水线型模数转换器

This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio(SNDR) and an 87.5 dB spurious-free dynamic range(SFDR) with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.