An improved AS-SCLF decoding algorithm of polar codes based on the assigned set

An improved successive cancellation list bit-flip based on assigned set (AS-SCLF) decoding algorithm is proposed to solve the problems that the successive decoding of the successive cancellation (SC) decoder has error propagation and the path extension of the successive cancellation list (SCL) decoder has the decision errors in the traditional cyclic redundancy check aided successive cancellation list (CA-SCL) decoding algorithm. The proposed algorithm constructs the AS firstly. The construction criterion is to use the Gaussian approximation principle to estimate the reliabilities of the polar subchannel and the error probabilities of the bits under SC decoding, and the normalized beliefs of the bits in actual decoding are obtained through the path metric under CA-SCL decoding, thus the error bits containing the SC state are identified and sorted in ascending order of the reliability. Then the SCLF decoding is performed. When the CA-SCL decoding fails for the first time, the decision results on the path of the SC state in the AS are exchanged. The simulation results show that compared with the CA-SCL decoding algorithm, the SCLF decoding algorithm based on the critical set and the decision post-processing decoding algorithm, the improved AS-SCLF decoding algorithm can improve the gain of about 0.29 dB, 0.22 dB and 0.1 dB respectively at the block error rate (BLER) of 10-4 and reduce the number of decoding at the low signal-to-noise ratio (SNR), thus the computational complexity is also reduced.     

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.     

一种低延迟极化码串行抵消译码器设计

为了克服5G移动通信系统中极化码串行抵消(SC)译码算法延迟高、计算复杂度高、硬件结构复杂度高等问题,基于冻结比特、冻结比特对和冻结区间等方式,提出了冻结比特设计模式.该设计模式包含基于冻结比特对的译码延迟和计算复杂度的分析方法.通过优先剪枝冻结比特结点的方式,进一步化简SC译码树,提高了搜索译码树的速度.码长为1 0...     

Systematic analysis of the decoding delay in multiview video

We present a framework for the analysis of the decoding delay in multiview video coding (MVC). We show that in real-time applications, an accurate estimation of the decoding delay is essential to achieve a minimum communication latency. As opposed to single-view codecs, the complexity of the multiview prediction structure and the parallel decoding of several views requires a systematic analysis of this decoding delay, which we solve using graph theory and a model of the decoder hardware architecture. Our framework assumes a decoder implementation in general purpose multi-core processors with multi-threading capabilities. For this hardware model, we show that frame processing times depend on the computational load of the decoder and we provide an iterative algorithm to compute jointly frame processing times and decoding delay. Finally, we show that decoding delay analysis can be applied to design decoders with the objective of minimizing the communication latency of the MVC system.     

极化码序列连续删除译码算法的改进设计

极化码连续删除译码算法性能和传统的LDPC码存在一定差距。序列连续删除算法(SCL)的提出极大地改善译码性能,是极化码推向实际应用中的重要一步。但是该算法复杂度较高,延迟大。改进的序列连续删除(SCL)译码算法是基于改善极化码码长受限的情况,文中描述SCL算法是通过码树上的搜索序列路径来表示译码过程。改进的算法通过减少译码算法在码树上的序列路径来降低时间和空间复杂度。通过仿真表明,改进的算法有效地降低了译码的复杂度同时在性能上也接近最大似然(ML)译码算法。     

Hardware Implementation for Bipartite Belief Propagation Polar Decoding with Bit Flipping

For the scenarios with high throughput requirements, the belief propagation (BP) decoding is one of the most promising decoding strategies for polar codes. By pruning the redundant variable nodes (VNs) and check nodes (CNs) in the original factor graph, the graph is condensed to a sparse bipartite graph that is similar to the graph for low-density parity-check (LDPC) codes. In this paper, we introduce the bit flipping scheme into the LDPC-like BP (L-BP) decoding and propose two methods to identify the error-prone VNs. By additional decoding attempts, the L-BP flip (L-BPF) decoding improves the error-correction performance with a similar average complexity for high E_b/N₀ values. The simulation results show that the L-BPF decoding achieves 0.25 dB gain compared with the L-BP decoding. Finally, a parallel decoder with the proposed L-BPF algorithm for an (256,128) polar code is implemented using 65nm CMOS technology, and it delivers a throughput of 1877.3 Mbps.

     

Successively Structured Gaussian Two-terminal Source Coding

Multiterminal source coding refers to separate encoding and joint decoding of multiple correlated sources. Joint decoding requires all the messages to be decoded simultaneously which is exponentially more complex than a sequence of single-message decodings. Inspired by previous work on successive coding, we apply the successive Wyner-Ziv coding, which is inherently a low complexity approach of obtaining a prescribed distortion, to the two-terminal source coding scheme. First, we consider 1-helper problem where one source provides partial side information to the decoder to help the reconstruction of the main source. Our results show that the successive coding strategy is an optimal strategy in the sense of achieving the rate-distortion function. By developing connections between source encoding and data fusion steps, it is shown that the whole rate-distortion region for the 2-terminal source coding problem is achievable using the successive coding strategy. Comparing the performance of the sequential coding with the performance of the successive coding, we show that there is no sum-rate loss when the side information is not available at the encoder. This result is of special interest in some applications such as video coding where there are processing and storage constraints at the encoder. Finally, we provide an achievable rate-distortion region for the m-terminal source coding.

基于SSCANL译码器的联合迭代检测译码算法

为了提升基于极化码的稀疏码多址接入（sparse code multiple access,SCMA）系统接收机性能,提出了基于简化软消除列表（simplify soft cancellation list,SSCANL）译码器的循环冗余校验（cyclic redundancy check,CRC）辅助联合迭代检测译码接收机方案。该方案中极化码译码器使用SSCANL译码算法,采用译码节点删除技术对软消除列表（soft cancellation list,SCANL）算法所需要的L次软消除译码（soft cancellation, SCAN）进行简化,通过近似删除冻结位节点,简化节点间软信息更新计算过程,从而降低译码算法的计算复杂度。仿真结果表明,SSCANL算法可获得与SCANL算法一致的性能,其计算复杂度与SCANL算法相比有所降低,码率越低,算法复杂度降低效果越好;且基于SSCANL译码器的CRC 辅助联合迭代检测译码接收机方案相较基于SCAN译码器的联合迭代检测译码（joint iterative detection and decoding based on SCAN decoder, JIDD-SCAN）方案、基于SCAN译码器的CRC辅助联合迭代检测译码（CRC aided joint iterative detection and decoding based on SCAN decoder,C-JIDD-SCAN）方案,在误码率为10^-4时,性能分别提升了约0.65 dB、0.59 dB。     

Optimized dynamic compilation of dataflow representations for multimedia applications

This paper proposes two optimization methods based on dataflow representations and dynamic compilation that enhance flexibility and performance of multimedia applications. These optimization methods are intended to be used in an adaptive decoding context, or, in other terms, where decoders have the ability to adapt their decoding processes according to a bitstream. This adaptation is made possible by coupling the decoding information to process a stream inside a coded stream. In this paper, we use dataflow representations from the upcoming MPEG Reconfigurable Media Coding (RMC) standard to supply the decoding information to adaptive decoders. The benefits claimed by MPEG RMC are a reuse of coding tools between different specifications of decoder and an execution scalability on different processing units with a single specification, which can target either hardware and/or software platforms. These benefits are not yet achievable in practice as these specifications are not used at the receiver side in MPEG RMC. We valid these benefits and propose two optimizations for the generation and the execution of dataflow models: the first optimization takes benefits of the reuse of coding tools to reduce the time to obtain—configure—enforceable decoders. The second provides an efficient, dynamic, and scalable execution according to the features of the execution platform. We show the practical impact of these two optimizations on two decoder representations compliant with the MPEG-4 part 2 Simple Profile standard and the MPEG-4 Advanced Video Coding standard. The results shows that configuration time can be reduced by 3 and the performance of decoders can be increased by 50 %.     

一种高资源效率的Fast-RCSC极化码译码器

针对现有极化码软输出译码器存在的高资源消耗与低资源效率,设计了一种快速低复杂度软取消(Fast Reduced Complexity Soft-Cancelation,Fast-RCSC)译码算法及其译码器硬件架构。Fast-RCSC算法对内部特殊结点进行完整计算,在减少译码周期的同时仍有较好译码性能。基于不同特殊结点公式之间存在相似性,进而通过对引入的特殊结点模块进行计算结果复用以及计算模块分时复用,减少特殊结点模块资源消耗。通过共用存储单元以及对不足存储单元数据宽度的数据进行合并,降低存储资源消耗。在华润上华(Central Semiconductor Manufacturing Corporation,CSMC)180nm工艺下综合结果表明,设计的译码器在码长为1024的情况下,面积为2.92mm²,资源效率为245.2Mbps/mm²,相比现有软输出译码器有不同程度的提升。     

CS-FSCL decoding algorithm of polar codes based on critical sets

In order to reduce the number of redundant candidate codewords generated by the fast successive cancellation list (FSCL) decoding algorithm for polar codes, a simplified FSCL decoding algorithm based on critical sets (CS-FSCL) of polar codes is proposed. The algorithm utilizes the number of information bits belonging to the CS in the special nodes, such as Rate-1 node, repetition (REP) node and single-parity-check (SPC) node, to constrain the number of the path splitting and avoid the generation of unnecessary candidate codewords, and thus the latency and computational complexity are reduced. Besides, the algorithm only flips the bits corresponding to the smaller log-likelihood ratio (LLR) values to generate the sub-maximum likelihood (sub-ML) decoding codewords and ensure the decoding performance. Simulation results show that for polar codes with the code length of 1 024, the code rates of 1/4, 1/2 and 3/4, the proposed CS-FSCL algorithm, compared with the conventional FSCL decoding algorithm, can achieve the same decoding performance, but reduce the latency and computational complexity at different list sizes. Specifically, under the list size of L=8, the code rates of R=1/2 and R=1/4, the latency is reduced by 33% and 13% and the computational complexity is reduced by 55% and 50%, respectively.     

Iterative Channel Estimation and Successive ICI Cancellation for OFDM Systems over Doubly Selective Channels

In orthogonal frequency division multiplexing systems, significant inter-carrier interference (ICI) caused by doubly selective channels make challenge for reliable reception. In this paper, channel estimation and ICI cancellation are considered jointly. Relying on the basis expansion model (BEM) of time-varying channel, the linear system model of transceiver is established, and the corresponding joint optimization of the transmitted data and BEM coefficients is formulated. Due to the separability of the data and BEM coefficients, we use cyclic minimizing technique to perform channel estimation and equalization alternately. This yields a linear minimum mean square-error (LMMSE) channel estimator and a block MMSE equalizer respectively. The block MMSE equalizer has complexity O(N ³), where N is the number of data subcarriers. To reduce the complexity, instead of equalizing all the data simultaneously, we consider estimating each data symbol successively. This idea results in the per subcarrier interference canceller with lower complexity O(N ²). Finally, an iterative receiver consisting of the data-aided LMMSE channel estimator and the successive interference canceller is developed. Simulation results show the scheme is effective over the channel with relatively large Doppler spread.     

Parallel High Throughput Soft-Output Sphere Decoding Algorithm

Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. To speed up the computation, we propose a scheme with multiple fixed complexity sphere decoders to construct a parallel soft-output fixed complexity sphere decoder (PFSD). The proposed decoder is highly parallel and has performance comparable to soft-output list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate that the PFSD algorithm can increase the throughput and reduce bit error rate of a soft-output solution in a 4 × 4 16-QAM system, and has superior performance compared to other soft decoders with comparable throughput and computation complexity. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can achieve up to 75 Mbps throughput for 4 × 4 64-QAM configuration at 100MHz with low control overhead.     

一种高速Viterbi译码器的设计与实现

Viterbi算法是卷积码的最优译码算法.设计并实现了一种高速(3,1,7)Viterbi译码器,该译码器由分支度量单元(BMU)、加比选单元(ACSU)、幸存路径存储单元(SMU)、控制单元(CU)组成.在StratixⅡ FPGA上实现、验证了该Viterbi译码器.验证结果表明,该译码器数据吞吐率达到231Mbit/s,在加性高斯白噪声(AWGN)信道下的误码率十分接近理论仿真值.与同类型Viterbi译码器比较,该译码器具有高速、硬件实现代价低的特点.     

Blind decoders for linear dispersion codes in downlink DS-CDMAsystems

Among many proposed space-time codes, the linear dispersion (LD) space-time codes possess many coding advantages and retain a simple decoding at the same time. An LD decoder combined with a blind subspace-based multiuser detector (MUD) is studied in the downlink of a DS-CDMA system. To further improve the performance, a subspace-based sphere decoding algorithm is proposed. Finally, a decimation-combining processing is applied to the proposed subspace-based blind decoders to reduce the complexity with only slight performance loss     

Soft multiuser decoding for vector quantization over a CDMA channel

An approach to optimal soft decoding for vector quantization (VQ) over a code-division multiple-access (CDMA) channel is presented. The decoder of the system is soft in the sense that the unquantized outputs of the matched filters are utilized directly for decoding (no decisions are taken), and optimal according to the minimum mean-squared error (MMSE) criterion. The derived decoder utilizes a priori source information and knowledge of the channel characteristics to combat channel noise and multiuser interference in an optimal fashion. Hadamard transform representations for the user VQs are employed in the derivation and for the implementation of the decoder. The advantages of this approach are emphasized. Suboptimal versions of the optimal decoder are also considered. Simulations show the soft decoders to outperform decoding based on maximum-likelihood (ML) multiuser detection. Furthermore, the suboptimal versions are demonstrated to perform close to the optimal, at a significantly lower complexity in the number of users. The introduced decoders are, moreover, shown to exhibit near-far resistance. Simulations also demonstrate that combined source-channel encoding, with joint source-channel and multiuser decoding, can significantly outperform a tandem source-channel coding scheme employing multiuser detection plus table lookup source decoding     

Implementation and performance of a turbo/MAP decoder

The implementation and performance of a turbo/MAP decoder are described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very-high-performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from four to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing) and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16-state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E_b/N₀ of 0⋅32 and −0⋅30 dB respectively for a BER of 10⁻⁵. BERs down to 10⁻⁷ were also achieved for a small increase in E_b/N₀. An efficient implementation of a continuous MAP decoder is also presented, along with a synchronization technique for turbo decoders. © 1998 John Wiley & Sons, Ltd.     

Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture

This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)² product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb/s optical fiber transmission systems.     

Neural network decoding of the block Markov superposition transmission

A neural network (NN)-based decoding algorithm of block Markov superposition transmission (BMST) was researched.The decoders of the basic code with different network structures and representations of training data were implemented using NN.Integrating the NN-based decoder of the basic code in an iterative manner,a sliding window decoding algorithm was presented.To analyze the bit error rate (BER) performance,the genie-aided (GA) lower bounds were presented.The NN-based decoding algorithm of the BMST provides a possible way to apply NN to decode long codes.That means the part of the conventional decoder could be replaced by the NN.Numerical results show that the NN-based decoder of basic code can achieve the BER performance of the maximum likelihood (ML) decoder.For the BMST codes,BER performance of the NN-based decoding algorithm matches well with the GA lower bound and exhibits an extra coding gain.     

Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications

Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile communications transceiver to counter channel degradation due to intersymbol interference, multipath dispersion, and thermal noise induced by electronic circuit devices. For low energy mobile wireless communications, it is highly desirable to incorporate a decoder which has a very low power consumption while achieving a high coding gain. In this paper, a sub-optimal low-complexity multi-stage pipeline decoder architecture for a powerful channel coding technique known as turbo-code is presented. The presented architecture avoids complex operations such as exponent and logarithmic computations. The turbo-code decoding algorithm is reformulated for an efficient VLSI implementation. Furthermore, the communication channel statistic estimation process has been completely eliminated. The architecture has been designed and implemented with the 0.6 m CMOS standard cell technology using Epoch computer aided design tool. The performance and the circuit complexity of the turbo-code decoder are evaluated and compared with the other types of well-known decoders. The power consumption of the low-complexity turbo-code decoder is comparable to that of the conventional convolutional-code decoder. However, the low-complexity turbo-code decoder has a significant coding gain over the conventional convolutional-code decoders and it is well suited for very low power applications.