Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Low-latency architectures for high-throughput rate Viterbi decoders

In this paper, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoders. The proposed method guarantees parallel paths between any two-trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers. It leads to regular and simple architecture for the Viterbi decoding algorithm. The look-ahead ACS computation latency of the proposed method increases logarithmically with respect to the look-ahead step (M) divided by the encoder constraint length (K) as opposed to linearly as in prior work. For a 4-state (i.e., K=3) convolutional code, the decoding latency of the Viterbi decoder using proposed method is reduced by 84%, at the expense of about 22% increase in hardware complexity, compared with conventional M-step look-ahead method with M=48 (where M is also the level of parallelism). The main advantage of our proposed design is that it has the least latency among all known look-ahead Viterbi decoders for a given level of parallelism.     

Low-latency and high-throughput software turbo decoders on multi-core architectures

Annals of Telecommunications - In the last few years, with the advent of a software-defined radio (SDR), the processor cores were stated to be an efficient solution to execute the physical layer...     

Practical charge-transfer amplifier design architectures for low-power flash A/D converters

Two improved charge-transfer amplifiers (CTAs), used as zero-static-bias comparator preamplifiers in flash analog-digital converters, are proposed. The first improvement eliminates the capacitive coupling at the amplifier input, reducing area and input capacitance. The second eliminates the need for a common-mode output reference voltage by deriving the common-mode output from a switched average of the power supplies. In the latter, nearly a full-scale input range is achieved while preserving the low-power low offset characteristics of earlier CTAs. Voltage comparator devices were constructed in 0.6-/spl mu/m double-poly, triple-metal CMOS to test the prototype CTA architectures. Input common-mode range and offset performance consistent with simulation data is demonstrated with a 10X reduction in input capacitance. Measured dynamic power dissipation on the order of 3-6 /spl mu/W/MSPS is observed. The experimental CTA preamplifiers occupy roughly 0.015 mm/sup 2/.     

Exploring approximations in 4- and 8- point DTT hardware architectures for low-power image compression

Due to the intensive use of discrete transforms in picture coding, the search for fast and power-efficient approaches for their hardware implementation gains importance. The Discrete Tchebichef Transform (DTT) represents a discrete class of the Chebyshev orthogonal polynomials, and it is an alternative for the Discrete Cosine Transform, commonly used in picture coding. High energy compaction and decorrelation are the main properties of the DTT. The state-of-the-art approximate DTT matrix is composed of 0, 1, ? 1, 2, and ? 2 coefficient values. In this work, we propose a new approximation for both the 4-point and 8-point integer DTT with better quality and power-efficiency. We explore the effects of coefficient truncation, whose values are 1/16, ? 1/16, 1/8, ? 1/8, 1/4, and ? 1/4. Considering operations with integers, the smaller values of coefficients causes truncation in the internal transform calculations and leads to smaller values for the non-diagonal residues, which reduces the non-orthogonality. We have also selectively pruned the rows of the state-of-the-art approximate DTT matrix. The results show that the proposed pruned approximate DTT hardwired solutions increases the maximum frequency up to 5%, minimizes circuit area by over 30%, with savings of up to 32.4% in power dissipation with a higher compression ratio and fewer quality losses in the compressed image, when compared with state-of-the-art approximate DTT hardware designs.     

Synthesis of folded pipelined architectures for multirate DSPalgorithms

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues. The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms     

Synthesis and functionalization of epitaxial quantum dot nanostructures for nanoelectronic architectures

We describe methods for assembly of quantum dots (QDs) into arrays of any symmetry, and methods for nanoscale doping of individual QDs. We have previously shown how the Ga⁺ focused ion beam (FIB) can template Si(1 0 0) surfaces for controlled Ge QD nucleation. Local Ga-induced reduction of the wetting layer thickness also suppresses QD nucleation away from the templating sites. This allows synthesis of arrays of any defined geometry and set of spatial frequencies, with positional control of each QD element to ca. 10 nm. We have also applied these methods to “quantum dot molecule” (QDM) structures, that comprise four QDs surrounding a central surface pit and that form spontaneously under conditions of limited adatom mobility in GeSi/Si(1 0 0). Again, the positions and spacings of the QDMs can be controlled by local FIB templating. This creates hierarchical order over multiple lengths scales, from ultra-small dimensions inaccessible to conventional lithography (i.e. nm for QD spacing to tens of nm for individual QD sizes), to much greater length scales (hundreds of μm) over which controlled arrays of QDMs can be fabricated. The ability to bring individual QDs in the QDM into very close proximity (of order nm) has potential applications to nanoelectronic architectures based on electron/hole tunneling or spin interactions. We are developing methods for electronic and magnetic functionalization of these nanostructures using a mass-selected FIB, where ions of different species can be separated from liquid metal alloy sources (e.g. Si from AuSi, B and As from PdAsB, and Mn and Ge from MnGe).     

EPON与WiMAX融合宽带接入方案的分析比较

文章分析了作为固定宽带接入与无线宽带接入代表的EPON和WiMAX两者融合的意义,以及相比传统单一接入方式的优势,阐述了三种基于EPON和WiMAX的有线与无线宽带接入融合系统的结构和相应的控制机制.在此基础上,分析比较了三种方案的特点,并指出了三种方案各自适合的应用场景.     

Synthesis of area-efficient and high-throughput rate data formatconverters

This paper proposes two design methodologies for synthesis of area-efficient data format converters (DFCs) with high throughput rate. DFCs are grouped into various classes according to the specification of design parameters. The first design methodology is suitable for design of many representative classes of DFCs. The designs using this methodology are based on a two-dimensional (2-D) architecture. They have maximum throughput rate and are area-efficient. Various design examples are shown to demonstrate improved performance, flexibility and usefulness of this design methodology. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, this methodology leads to compact designs. The second design methodology employs an architecture using dual buffers. The simple and regular architecture using dual buffers leads to area-efficient DFCs. The design procedure using this methodology is simple and can reduce the design effort in many applications     

A comparison of fault-tolerant state machine architectures forspace-borne electronics

Very large scale integrated (VLSI) circuits used in the space and nuclear industry are continuously subjected to ion radiation. As the limits of VLSI technology are pushed towards sub-micron levels in order to achieve higher levels of integration, devices become more vulnerable to radiation induced errors. These radiation induced errors can lead to system failure, particularly if they affect the memory portion of vital subsystems, such as state machine controllers. This paper explores the use of classical fault-tolerant state machine architectures based on hardware and information redundancy to design radiation-immune controllers. Those architectures particularly suitable for VLSI-implementation using ordinary low power CMOS technology are identified, with the primary objective of correcting single flip-flop errors. Each architecture was implemented on a set of benchmark sequential circuits and evaluated in terms of circuit-size and maximum path-delay. The best overall architectures, `SEU-I TMR' and `Modified Explicit EC', used a nonredundant excitation circuit and redundant flip-flops, followed by error correction circuitry to tolerate single flip-flop errors     

A performance comparison of two p-i-n FET receiver circuit architectures

Two conceptually different p-i-n FET receiver circuit architectures are evaluated using a SPICE circuit simulation. The popular p-i-n FET transimpedance amplifier is compared to a new architecture that uses distributed gain and dual feedback. To highlight the importance of circuit architecture to receiver performance, identical device parameters are used in each circuit model. Frequency, phase, and pulse responses are computed and presented in graphical form. Results demonstrate that the popular receiver is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion.     

A performance comparison of two p-i-n FET receiver circuit architectures

Two conceptually different p-i-n FET receiver circuit architectures are evaluated using a SPICE circuit simulation. The popular p-i-n FET transimpedance amplifier is compared to a new architecture that uses distributed gain and dual feedback. To highlight the importance of circuit architecture to receiver performance, identical device parameters are used in each circuit model. Frequency, phase, and pulse responses are computed and presented in graphical form. Results demonstrate that the popular receiver is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion.     

Performance comparison of switch architectures with shareable parallel memory modules

The class of switches with shareable parallel memory modules include those switches that use parallel memory modules which are physically separate but logically shared. The two main classes of such architectures namely the Shared Multibuffer (SMB) based switch and the Sliding-Window (SW) based packet switch both deploy shareable parallel memory modules, however they differ in the switching scheme used by them to store incoming packets and transfer packets among different switch ports. In this letter, we investigate and compare the performance of switching schemes deployed by these two classes of switching architectures. We compare throughput and packet loss performance of these two switches under conditions of identical traffic type, switch configuration and memory resource deployed.     

Synthesis of control circuits in folded pipelined DSP architectures

A systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified technology constraints, is presented. The folding set specifies the processor and the time partition at which the task is executed and is typically obtained by performing scheduling and resource allocation for the algorithm data-flow graph and the specified iteration period. The constraints imposed on the hardware architecture are also assumed to be known. The technique is used to derive the control circuitry of the hardware architecture. The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators. They propose automatic retiming and pipelining of algorithms described by data-flow graphs for folding. The folding algorithm is applied after preprocessing the data-flow graph for automated pipelining and retiming     

High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

基于SSIM和SAD的AVS帧内预测模式改进算法

在AVS帧内预测模式的选择过程中,以绝对误差和(SAD)作为失真度量,通过相应的i_sad代价函数进行选择,但是这种方法被证明不能很好地符合人眼视觉(HVS).由于结构相似度(SSIM)算法相对简单,准确性好,优于传统的PSNR等方法,因此提出了将SSIM和SAD作为帧内预测模式选择的标准.实验表明,将SSIM和SAD用于AVS帧内预测模式选择,获得了比原AVS更好的重建图像质量和更高的编码压缩率.     

The switching-activity estimation of SAD engine for video coding systems

The sum of absolute difference (SAD) is generally adopted as a cost function in motion estimation (ME) and temporal error concealment (TEC) algorithm owing to its efficiency. The hardware architecture of SAD also consumes considerable power dissipation in video codec chip. Hence, the switching-activity analysis on SAD is quite essential from algorithm/architecture perspectives. This work develops the estimation formulas for switching-activity dedicated for SAD engine according to probability theory. The experiment results reveal that the probability error rate (PER) of the SAD engine is as minor as 5.61%. Consequently, this leads to a precise switching-activity estimation of the SAD-based algorithm/architecture for video signal processing.     

Gb接口使用率测算方法的比较分析及扩容方案

在通讯设备的更新换代中,作为数据通信关键链路的Gb接口在什么状况下需要扩容一直是焦点.文中针对寻找最佳Gb接口扩容方案的目的,通过对Gb接口的使用率测算方案的分析比较,得出Gb接口扩容的标准及扩容方案,应在Bssgp层,使用bssgpDownlinkOctets命令来计算计数器的个数,准确记录每个BSC对应的Gb接口的使用状况,具体到某个BSC节点的扩容建议,然后采取扩展BSC节点时隙,扩容E1T1板.经现网升级过程中应用,取得了良好的效果.