ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al(2)O(3) gate oxides

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al(2)O(3) tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8?V was observed in its drain current versus gate voltage (I(DS)-V(GS)) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.     

Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.     

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.     

Massive assembly of ZnO nanowire-based integrated devices

Although a directed assembly strategy has been utilized for the massive assembly of various nanowires and nanotubes (NWs/NTs), its application has usually been limited to rather small-diameter NWs/NTs prepared in solution. We report two complementary methods for the massive assembly of large-size ZnO nanowires (NWs). In the solution-phase method, ZnO NWs were assembled and aligned selectively onto negatively charged surface patterns in solution. In addition, the substrate bias voltage and capillary forces can be used to further enhance the adsorption rate and degree of alignment of ZnO NWs, respectively. In the direct-transfer method, a NW film grown on a solid substrate was placed in close proximity to?a?molecule-patterned substrate, and ultrasonic vibration was applied so that the NWs were directly transferred and aligned onto the patterned substrate. The solution-phase and direct-transfer methods are complementary to each other and suitable for the assembly of NWs?prepared in solution and on solid substrates, respectively.     

The fabrication and application of Ni-DNA nanowire-based nanoelectronic devices

DNA is a self-assembled, double stranded natural molecule that can chelate and align nickel ions between its base pairs. The fabrication of a DNA-guided nickel ion chain (Ni-DNA) device was successful, as indicated by the conducting currents exhibiting a Ni ion redox reaction-driven negative differential resistance effect, a property unique to mem-elements (1). The redox state of nickel ions in the Ni-DNA device is programmable by applying an external bias with different polarities and writing times (2). The multiple states of Ni-DNA-based memristive and memcapacitive systems were characterized (3). As such, the development of Ni-DNA nanowire device-based circuits in the near future is proposed.

     

Fabrication process for ion-implanted and Permalloy hybrid magneticbubble memory devices

A fabrication process for ion-implanted and Permalloy hybrid bubble memory devices has been developed. The mask patterns of polyimide (PIQ) for ion-implanted tracks are fabricated using a tri-level resist process where the top imaging resists are delineated by deep UV contact printing. The minimum feature of the PIQ pattern is 0.75 μm and can be controlled precisely. The sidewalls of PIQ patterns are smooth and vertical. At the junctions between ion-implanted and Permalloy tracks, tapered resist patterns are used as masks for implantation. Novolak-based resist is used and is reflowed thermally to obtain a tapered profile. Fabrication conditions, such as type of resist and baking temperature, were investigated to achieve good reproducibility. Tapered resist patterns are also used as masks for iron milling which reduces the thickness of garnet film in the area of the Permalloy tracks. This is necessary to adjust the operating bias field of Permalloy tracks to that of the ion-implanted tracks. A prototype of a 4-Mb memory device was fabricated, confirming the feasibility of the present process     

Polymer-ultrathin graphite sheet-polymer composite structured flexible nonvolatile bistable organic memory devices

We present data, which were obtained before bending and after bending, for the electrical bistabilities, memory stabilities, and memory mechanisms of three-layer structured flexible bistable organic memory (BOM) devices, which were fabricated utilizing the ultrathin graphite sheets (UGS) sandwiched between insulating poly(methylmethacrylate) (PMMA) polymer layers. The UGS were formed by transferring UGS (about 30 layers) and using a simple spin-coating technique. Transmission electron microscopy (TEM) measurements were performed to investigate the microstructural properties of the PMMA/UGS/PMMA films. Current-voltage (I-V) measurements were carried out to investigate the electrical properties of the BOM devices containing the UGS embedded in the PMMA polymer. Current-time (I-t) and current-cycle measurements under flat and bent conditions were performed to investigate the memory stabilities of the BOM devices. The memory characteristics of the BOM maintained similar device efficiencies after bending and were stable during repeated bendings of the BOM devices. The mechanisms for these characteristics of the fabricated BOM are described on the basis of the I-V results.     

A study of cycling induced degradation mechanisms in Si nanocrystal memory devices

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.     

Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.     

Controlled deposition of new organic ultrathin film as a gate dielectric layer for advanced flexible capacitor devices

This letter describes a new organic (1-bromoadamantane) ultrathin film as gate dielectric, which was successfully deposited by sol–gel spin-coating process on a flexible polyimide substrate at room temperature. The metal–insulator-metal (MIM) device with organic (1-bromoadamantane) ultrathin (10 nm) film as gate dielectric layer operated at gate voltage of 5.0 V, showing a low leakage current density (5.63 × 10^?10 A cm^?2 at 5 V) and good capacitance (2.01 fF μm^?2 at 1 MHz). The chemical structure of the 1-bromoadamantane layer was investigated by Fourier transform infrared spectrometer. The excellent leakage current density and better capacitance, probably due to the presence of polar, non-polar, low-polar groups, and bromine atoms in ultrathin film. Practical properties of the film in MIM capacitor such as dielectric constant as well as bending result of leakage current density and breakdown voltage have been better related to such fundamental adhesion nature over flexible substrate. This permits estimation of the properties of new dielectric in thin film form and short lists of the best materials for low loss and good capacitance flexible capacitors could be drawn up in future.     

Interrogation of extrinsic Fabry-Perot interferometric sensors using arrayed waveguide grating devices

In this paper, we present details of a solid state interrogation system based on a 16-channel arrayed waveguide grating (AWG) for interrogation of extrinsic Fabry-Perot interferometric sensors. The sensing element is configured in a reflecting mode and is illuminated by a broad-band light source through an optical fiber. The spectrum of light reflected from the sensor is analyzed using an AWG device acting as a coarse spectrometer. Using measurement points from the AWG channels, the original spectrum of the sensing element is reconstructed by a means of curve fitting. This allows sufficient information for the position of the reflection peak (or inverted peak) to be uniquely determined and the value of a measurement quantity obtained. In addition to the theoretical simulations of the proposed measurement system, we provide details of the laboratory evaluation.     

一种超薄硅薄膜的制作方法

超薄、平整的硅应变薄膜对于制作低量程的电容式压力传感器是非常重要的。提出一种简单的超薄薄膜制作方法，利用浓硼扩散、KOH自停止腐蚀和LPCVD等关键技术，得到了厚度4μm左右的平整的Si(P )/Si3N4复合薄膜。由于内应力引起的挠度在几百纳米数量级，为制作压力传感器奠定了有用的工艺基础。     

Cu2ZnSnS4/Si异质结器件的制备及特性研究

利用脉冲激光沉积法在不同电阻率的n型Si(100)基片上沉积Cu2ZnSnS4薄膜,制备p-Cu2ZnSnS4/n-Si异质结.利用X射线衍射(XRD)、X射线能谱(EDS)和原子力显微镜(AFM)对Cu2ZnSnS4薄膜的结构、组分和形貌进行表征,并对器件进行I-V测试,讨论不同电阻率的Si对异质结器件光电特性的影响.结果表明,器件有良好的整流特性,Si电阻率大的器件光电响应比较好,而Si电阻率小的器件光伏效应比较明显.     

Fabrication of quantum-dot devices in graphene

Abstract

We describe our recent experimental results on the fabrication of quantum-dot devices in a graphene-based two-dimensional system. Graphene samples were prepared by micromechanical cleavage of graphite crystals on a SiO₂/Si substrate. We performed micro-Raman spectroscopy measurements to determine the number of layers of graphene flakes during the device fabrication process. By applying a nanofabrication process to the identified graphene flakes, we prepared a double-quantum-dot device structure comprising two lateral quantum dots coupled in series. Measurements of low-temperature electrical transport show the device to be a series-coupled double-dot system with varied interdot tunnel coupling, the strength of which changes continuously and non-monotonically as a function of gate voltage.     

SOI射频集成器件研制

提出了包含射频有源和无源器件的sOI集成结构及工艺方案,在同一SIMOX衬底上制作了射频LDMOS、NMOS、电感、电容、电阻和变容管。核心的LDMOS、NMOS和电感器件均获得了优良的电学特性：0．25μm栅长的LDMOS截止频率和关态击穿电压分别为19．3GHz和16．1V;而0．25μm栅长的NMOS对应参数则为21．3GHz和4．8V;采用开发的局部介质增厚技术后,2nH、5nH、10nH螺旋电感的最大品质因数分别达到了6．5、5．0、4．0,相对于不采用此技术的电感(最大品质因数分别为4．3、3．2、2．3),分别改善了77％,58％,49％。     

Fabrication of bubble memory chips

Investigations have been made on the fabrication of accurate and uniform T-bar circuits. Chrome masks are preferable to emulsion masks, and furthermore, a minimum exposure and intimate contact have been demonstrated to be necessary for accurate and uniform pattern imaging on the AZ1350 resist. A newly developed chemical etchant, a nitric acid-base solution without ferric chloride, can almost eliminate undercutting of permalloy elements. Application of spin-on-glass prior to Permalloy evaporation can result in excellent step coverage at the places where T-bar circuits overlap conductors. Large memory chips having a capacity of 16 × 10³bits and a storage density of 10⁵bits/cm²have successfully been fabricated.     

Memory effects of nonvolatile memory devices with a floating gate fabricated utilizing Ag nanoparticles embedded into a polymethylmethacrylate layer

Nonvolatile memory devices based on a polymethylmethacrylate (PMMA) layer containing Ag nanoparticles were formed by using a spin coating method. High-resolution transmission electron microscopy images showed that Ag nanoparticles were randomly distributed in the PMMA layer. Capacitance-voltage (C-V) curves for the Al/Ag nanoparticles embedded in a PMMA layer/p-Si(100) device at 300 K showed a hysteresis with a large flat-band voltage shift, indicative of the Ag nanoparticles acting as the charge storage in the memory device. The magnitude of the flat-band voltage shift for the memory devices increased with increasing Ag nanoparticle concentration. The operating mechanisms for the writing and the erasing processes for the Al/Ag nanoparticles embedded in a PMMA layer/p-Si(100) device are described on the basis of the C-V results and electronic structures.     

基于导电纤维的柔性电子器件研究进展

柔性电子器件具有优异的灵活性,实现了与服装的无缝集成,在各种实际的可穿戴应用中具有巨大的潜力。一维纤维状电子器件由于其优异的柔韧性、可编织性及舒适性成为智能可穿戴领域的研究热点。首先,综述了用于纤维状柔性电子器件的一维可拉伸电极的研究进展,然后详细介绍了高性能一维纤维状柔性电子器件制备过程中具有代表性的导电材料、制造技术及一维柔性纤维进一步应用于各类电子器件的主要制备方法,另外总结了近年来基于柔性纤维状电子器件在智能可穿戴领域的应用。最后对一维纤维基智能可穿戴电子器件的机遇和挑战进行了批判性思考。      

自对准栅型谐振隧穿晶体管试制

针对谐振隧穿二极管(RTD)在通用电路应用中的局限性,提出并设计了自对准栅型谐振隧穿晶体管结构,进行了材料的分子束外延,采用传统湿法腐蚀、金属剥离、台面隔离和空气桥互连工艺,初步研制出具有较明显栅控能力的谐振隧穿晶体管(RTT)单管,其峰值电流密度高达80.8 kA/cm2,峰谷电流比为3.6,负阻阻值在20Ω左右.研究还发现,器件的峰值电流随栅压增大而减小,谷值电流随栅压增大而增大,而且出现零点分离.这些现象与栅的纵向位置控制不当有关,可以通过减小栅间发射极宽度,缩短栅与势垒层距离,和减小发射层掺杂浓度得到改善.     

Fabrication and performance of GaN electronic devices

GaN and related materials (especially AlGaN) have recently attracted a lot of interest for applications in high power electronics capable of operation at elevated temperatures. Although the growth and processing technology for SiC, the other viable wide bandgap semiconductor material, is more mature, the AlGaInN system offers numerous advantages. These include wider bandgaps, good transport properties, the availability of heterostructures (particularly AlGaN/GaN), the experience base gained by the commercialization of GaN-based laser and light-emitting diodes and the existence of a high growth rate epitaxial method (hydride vapor phase epitaxy) for producing very thick layers or even quasi-substrates. These attributes have led to rapid progress in the realization of a broad range of GaN electronic devices, including heterostructure field effect transistors (HFETs), Schottky and p–i–n rectifiers, heterojunction bipolar transistors (HBTs), bipolar junction transistors (BJTs) and metal-oxide semiconductor field effect transistors (MOSFETs). This review focuses on the development of fabrication processes for these devices and the current state-of-the-art in device performance, for all of these structures. We also detail areas where more work is needed, such as reducing defect densities and purity of epitaxial layers, the need for substrates and improved oxides and insulators, improved p-type doping and contacts and an understanding of the basic growth mechanisms.