14-b400-ksps 2.5-mW连续时间Σ-Δ调制器

连续时间Σ-Δ调制器较之传统的开关电容Σ-Δ调制器具有更低的功耗、更小的面积,以及集成抗混叠滤波器等诸多优势。设计了一种应用于低中频GSM接收机的4阶单环单比特结构的连续时间Σ-Δ调制器。在调制器中,采用了开关电容D/A转换器,以降低时钟抖动对性能的影响。仿真结果显示,在1.8 V工作电压2、00 kHz信号带宽、0.18μm CMOS工艺条件下,采样频率21 MHz,动态范围(DR)超过90 dB,功耗不超过2.5 mW。     

低电压Σ-Δ调制器关键技术及设计实例

介绍了低电压开关电容Σ-Δ调制器的实现难点及解决方案,并设计了一种1 V工作电压的Σ-Δ调制器.在0.18 μm CMOS工艺下,该Σ-Δ调制器采样频率为6.25 MHz,过采样比为156,信号带宽为20 kHz;在输入信号为5.149 kHz时,仿真得到Σ-Δ调制器的峰值信号噪声失真比达到102 dB,功耗约为5 mW.     

高速二阶∑-△A/D调制器的设计

文章对二阶Σ-ΔA/D调制器的原理、系统性能及稳定性进行了分析,给出噪声传递函数和信噪比。并根据实际的器件参数和设计准则,应用CMOS开关电容和高速模拟电路技术,用0.6μm工艺实现了一个高速二阶Σ-Δ调制器。     

Σ-Δ调制器的非理想特性行为级建模与仿真

分析了开关电容型(SC)Σ-Δ调制器的非理想特性,主要包括采样时钟抖动、开关热噪声(kT/C噪声)、运放增益等。在建立各自噪声模型的基础上,构造了一个二阶有色噪声和一个四阶白噪声Σ-Δ调制器模型;通过仿真结果的比较,在行为级上验证了噪声模型的正确性,所建电路更为实际地描述了Σ-Δ调制器的各项参数。     

基于开关电容技术的Σ-Δ调制器的设计

基于0.18μm标准CMOS工艺,设计并实现了一个单环三阶开关电容Σ-Δ调制器。电路采用具有加权前馈求和网络的积分器级联型拓扑结构,采用优化的具有正反馈的单级A类OTA来降低功耗。在设计中,采用电流优化技术来降低运算跨导放大器(OTA)的功耗。Σ-Δ调制器的过采样率为128,时钟频率为6.144 MHz,信号带宽为24 kHz,最大信噪比为100 dB,动态范围为103 dB。电路在1.8 V电源供电下功耗为2.87 mW。     

一种适用于数字音频的Δ-ΣD/A转换器

设计了一种适于数字音频应用的18位48 kHz Δ-Σ D/A转换器.其内插滤波器采用时分复用和无需乘法器的设计,降低了硬件开销.Δ-Σ调制器采用5阶单环单比特量化结构,经FPGA平台验证,可实现100 dB的带内信噪比.开关电容(SC)重建滤波器采用CSMC 0.6 μm CMOS工艺实现,核心芯片面积为1.73 mm×1.11 mm,在5 V工作电源下,其功耗小于22 mW.     

一种0.18m单层多晶硅CMOS音频-调制器

设计了一种应用于18位高精度音频模数转换器(ADC)的三阶Σ-Δ调制器。调制器采用2-1级联结构,优化积分器的增益来提高调制器的动态范围。采用栅源自举技术设计输入信号采样开关,有效提高了采样电路的线性度。芯片采用中芯国际0.18μm混合信号CMOS工艺,在单层多晶硅条件的限制下,采用MIM电容,实现了高精度的Σ-Δ调制器电路。测试结果表明,在22.05kHz带宽内,信噪失真比(SNDR)和动态范围(DR)分别达到90dB和94dB。     

一种斩波稳定低噪声Σ-Δ调制器设计

针对Σ-Δ调制器输入失调电压的需求,设计了一种新型低输入失调电压的Σ-Δ调制器。利用斩波稳定运算放大器和新颖的开关电容积分器,动态消除了直流失调电压以及低频噪声(主要包含1/f噪声),使得调制器的输入失调电压微乎其微。基于0.15 μm CMOS工艺,利用Hspice软件对电路进行仿真,同时采用Matlab和TCL对仿真结果进行分析。仿真结果表明,在电源电压为4.5~5.5 V、温度为-40 ℃~85 ℃、各种工艺角下,低频噪声抑制能力增加了15 dB,且当运算跨导放大器的失调电压为10 mV时,Σ-Δ调制器的输入失调电压由9.7 mV下降为0.4 mV。     

一种完全前馈式单环多位Σ-Δ调制器

采用0.18 μm CMOS工艺,设计了一款可用于UHF RFID阅读器芯片接收链路的Σ-Δ调制器。该调制器采用单环3阶4位量化结构,由开关电容电路实现。在过采样率为16的情况下,调制器能够处理大于-2 dBFS的输入信号,在1.5 MHz信号带宽内,达到12位以上的有效分辨率。整个调制器在3.3 V工作电压下消耗5 mA电流。     

一种级间运放共享的MASH结构Σ-Δ调制器

基于55 nm CMOS工艺,设计了一种级间运放共享的级联噪声整形(MASH)结构Σ-Δ调制器。采用2-2 MASH结构对调制器参数进行了设计。对经典结构的开关电容积分器进行了改进,并应用到调制器电路的设计中,实现了两级调制器之间的运放共享,在达到高精度的同时减少了运放的数量,显著降低了MASH结构调制器的功耗。仿真结果表明,在3.3 V电源电压下,调制器信噪失真比为111.7 dB,无杂散动态范围为113.6 dB,整体功耗为16.84 mW。     

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.     

A 40-μA/channel compensated 18-channel strain gauge measurementsystem for stress monitoring in dental implants

This paper presents an autonomous monitoring system ASIC, which is capable of measuring and compensating 18 strain gauges simultaneously. This sensor interface is implemented in a 0.7-μm CMOS technology and includes a proportional to absolute temperature (PTAT)-current reference, an 8-bit digital-to-analog converter together with a digital interface for multigauge nulling, a switched-capacitor (SC) instrumentation amplifier, an SC sample-and-hold (S/H), and a 9-bit successive approximation analog-to-digital converter. The total chip consumes a mere 40 μA/channel (at 3.1 V) and allows for sampling of each individual strain gauge channel at a sampling rate of 111 Hz with a 20-μstrain accuracy. The measurement system presented is a part of an autonomous data logger, which is integrated in a dental prosthesis     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

提高读出电路输入电流动态范围的新方法

设计了一个由CMOS差分放大器构成的电容反馈跨阻型紫外焦平面单元读出电路。该电路在传统的读出电路基础上进行改进,大幅度的提高了输入电流的动态范围。该单元读出电路可应用于工作在快照模式下的128×128FPA读出电路,像素输出速率达10MHz,为探测器提供0．3V～2V的稳定偏置电压,输入电流的动态范围达52dB。     

A low power consumption CMOS differential-ring VCO for a wireless sensor

This paper describes a new three-stage voltage controlled ring oscillator (VCO) based on 0.35???m standard CMOS technology. The VCO was designed for a transmitter operating in the 863?C870?MHz European band for wireless sensor applications. The transmitter is designed for binary frequency-shift keying (BFSK) modulation, communicating a maximum data rate of 20?kb/s. In addition to the VCO, the transmitter combines a BFSK modulator, an up conversion mixer, a power amplifier and an 863?C870?MHz band pass filter. The modulator uses the frequency hopping spread spectrum and it is intended for short range wireless applications, such as wireless sensor networks. The oscillation frequency of the VCO is controlled by a voltage V_CTRL. Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 3.3?V, is only 7.48?mW. The proposed VCO exhibits a phase noise lower than ?126?dBc/Hz at 10?MHz offset frequency.     

A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters

This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-AB topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 at the switching frequency attenuating the output ripple voltage to less than 12 . A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 0.35 m CMOS process and occupies an area of 4.7 .     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

基于不同VTH值的新型CMOS电压基准

传统基准电路主要采用带隙基准方案,利用二级管PN结具有负温度系数的正向电压和具有正温度系数的yBE电压得出具有零温度系数的基准。针对BJT不能与标准的CMOS工艺兼容的缺陷,利用NMOS和PMOS管的两个阈值电压VTHN和VTHP具有相同方向但不同数量的温度系数,设计了一种基于不同VTH。值的新型CMOS基准。该电路具有没有放大器、没有BJT、结构简单等特点,适宜于标准CMOS工艺集成。在此给出了详细的原理分析和电路实现。该电路通过HSpice验证,其输出基准电压为1．22V,在-40～＋85℃内温度系数仅为30ppm／℃,电源电压为2．6～5．5V时,电源电压调整率为1．996mV／V。     

一种应用于CMOS图像传感器的片上内插式ADC设计

设计了一种用于1024×1024CMOS图像传感器的内插式模数转换器（ADC）结构。转换采用并行处理方式,采用内插式结构,与流水线ADC相比速度更快。电路采用失调纠正技术和衬底驱动技术设计了1个低失调电压的前置全差分两级跨导运算放大器（OTA）,PMOS管作为电阻产生与锁存阈值电压相交的基准电压,具有较高的精度。基于0．35μmCMOS工艺的仿真结果表明,该ADC的DNL=0．45LSB,INL=0．65LSB,可以满足CMOS图像传感器芯片级ADC的高速高精度要求。     

开关式低压CMOS温度传感器的设计与实现

介绍了一种基于0.18μm CMOS工艺,具有开关功能的低压集成温度传感器。该温度传感器利用半导体pn结的电流电压与温度有关的特性,获取双极晶体管基极-发射极电压差值ΔVBE,采用仪表放大器进行后级放大。仪表放大器由两个采用折叠式共源共栅结构,带有PD开关信号的运算放大器作为反馈系统,放大倍数为7。用ADE工具,对整个电路在工作电压1.8 V、偏置电流20μA下进行仿真,得到其精度为1.58 mV/℃,再在不同工艺角下进行仿真验证。版图总面积为320μm×280μm。该设计已经在一款数字视频芯片中得到实现,用于实时检测芯片温度。实际测试结果与模拟仿真结果基本相同。