Substrate and Device Pattern Dependence of the Thermal Crosstalk in Y Ba2Cu 3O7−δ Transition Edge Bolometer Arrays

Using YBa₂Cu₃O_7-delta (YBCO) thin films, pulsed laser deposited on 1-mm-thick LaAlO₃ or SrTiO₃ substrates, we made 4times1 pixel arrays of transition edge bolometers with separations between neighboring pixels ranging from 40 mum to 170 mum for testing purposes. We investigated the effects of the YBCO film thickness (200 and 400 nm), substrate material, and back-etching of the substrate, on the crosstalk between the pixels of the arrays. The investigation was based on the analysis of the voltage response of the dc current biased bolometers versus the modulation frequency of a near-infrared laser source. We observed that the bolometer arrays made of 400-nm-thick films had less interpixel thermal crosstalk than the 200-nm-thick films. The effect of substrate thickness on the response of the pixels was investigated by up to 500 mum back-etching of the substrates. The bolometers made on back-etched LaAlO₃ substrates had anomalous crosstalk response behavior, which was effective at higher modulation frequencies. In addition, we present an analytical thermal model for explaining the observed effects of the thermal crosstalk on the response characteristics of the pixels of the arrays. We report the measured response and the anticipated thermal crosstalk of the characterized bolometers'. We describe the responses based on the thermal models and discrepancies from the model's predictions     

Fabrication and characterization of 100-nm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As double-gate HEMTs with two separate gate controls

In this letter, we demonstrate successful operation of 100-nm T-gates double-gate high electron mobility transistors with two separate gate controls (V/sub g1s/ /spl ne/ V/sub g2s/). These devices are fabricated by means of adhesive bonding technique using enzocyclocbutene polymer. The additional gate enables the variation of the threshold voltage V/sub th/ in a wide range from -0.68 to -0.12V while keeping high cutoff frequency f/sub t/ of about 170 GHz and high maximum oscillation frequency f/sub max/ of about 200 GHz. These devices are considered as being very effective for millimeter-wave mixing applications and are promising devices for the fabrication of velocity modulation transistor (VMT) (Sakaki et al., 1982).     

0.6-eV bandgap In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic devices grown on InAs/sub y/P/sub 1-y/ step-graded buffers by molecular beam epitaxy

Single-junction, lattice-mismatched (LMM) In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic (TPV) devices with bandgaps of 0.60 eV were grown on InP substrates by solid-source molecular beam epitaxy (MBE). Step-graded InAs/sub y/P/sub 1-y/ buffer layers with a total thickness of 1.6 /spl mu/m were used to mitigate the effects of 1.1% lattice mismatch between the device layer and the InP substrate. High-performance single-junction devices were achieved, with an open-circuit voltage of 0.357 V and a fill factor of 68.1% measured at a short-circuit current density of 1.18 A/cm/sup 2/ under high-intensity, low emissivity white light illumination. Device performance uniformity was outstanding, measuring to better than 1.0% across a 2-in diameter InP wafer indicating the promise of MBE growth for large area TPV device arrays.     

Limitation of DC currents by YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta//-Au superconducting films

The limitation of dc fault currents is one of the issues for the development of dc networks or links. This paper shows for the first time the high potential of YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta//-Au bilayers for the design of dc current limiters. Such devices are based on the transition into the normal state of the superconducting YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// films above a current I/sup */>I/sub c/, where I/sub c/ is the critical current at the onset of dissipation. The study of the transition under current pulses shows that a thermally driven transition into the normal state can occur after a delay t/sub trans/. This duration is defined by the amplitude of the current pulse. For I/sup *//spl ap/3I/sub c/, this delay is less than 10 /spl mu/s. The abrupt transition into the normal state allows an efficient current limitation. A recovery of the superconducting state can also occur under current. This property can be extremely interesting for autonomous operation of a current limiter in an electrical network in case of transient over-currents coming from the starting of high-power devices.     

The thermal stability of one-transistor ferroelectric memory with Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-poly-SiO/sub 2/-Si gate stack

The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-Poly-SiO/sub 2/-Si was characterized in the temperature range of -10/spl deg/C to 150/spl deg/C. The memory windows decrease when the temperatures are higher than 60/spl deg/C. The drain currents (I/sub D/) after programming to on state decrease with increasing temperature. The drain currents (I/sub D/) after programming to off state increase with increasing temperature. The ratio of drain current (I/sub D/) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150/spl deg/C. On the other hand, the memory window and the ratio of I/sub D/(on)/I/sub D/(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10/spl deg/C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60/spl deg/C.     

Acoustically actuated flextensional Si/sub x/N/sub y/ and single-crystal silicon 2-D micromachined ejector arrays

We propose using two-dimensional (2-D) micromachined droplet ejector arrays for environmentally benign deposition of photoresist and other spin-on materials, such as low-k and high-k dielectrics used in IC manufacturing. Direct deposition of these chemicals will reduce waste as well as production cost. The proposed device does not harm heat or pressure sensitive fluids and they are chemically compatible with the materials used in IC manufacturing. Each element of the 2-D ejector array consists of a flexurally vibrating circular membrane on one face of a cylindrical fluid reservoir. The membrane has an orifice at the center. A piezoelectric transducer generating ultrasonic waves, located at the open face of the reservoir, actuates the membranes. As a result of this actuation, droplets are fired through the membrane orifice. Ejector arrays were built with either Si/sub x/N/sub y/ or single-crystal silicon membranes using two different fabrication processes. We show that single-crystal silicon membranes are more uniform in their thickness and material quality than those of Si/sub x/N/sub y/ membranes. The single-crystal silicon membrane-based devices showed thickness and material uniformity across all the membranes of an array. This improvement eliminated nonuniform membrane resonance frequencies across an array as observed with Si/sub x/N/sub y/ membrane-based devices. Therefore, it should be possible to repeatably build devices and to predict their dynamic characteristics. Using the fabricated devices, we demonstrated water ejection at 470 kHz, 1.24 MHz, and 2.26 MHz. The corresponding droplet diameters were 6.5, 5, and 3.5 /spl mu/m, respectively.     

Speed limit of all-optical gate switches using cascaded second-order nonlinear effect in quasi-phase-matched LiNbO/sub 3/ devices

In all-optical gate switches that employ the cascaded second-order nonlinear effect in quasi-phase-matched (QPM) LiNbO/sub 3/ devices, walkoff between the fundamental and second harmonic pulses is very large. The authors experimentally show that crosstalk of the switch induced by such walkoff limits the switching speed, but that the switching speed can significantly be enhanced by walkoff compensation. Using a 20-mm-long QPM LiNbO/sub 3/ waveguide device, the authors switch one of twin pulses separated by 6.25 ps without crosstalk, showing the possibility of switching a 160-Gb/s signal.     

Highly linear Al/sub 0.3/Ga/sub 0.7/N-Al/sub 0.05/Ga/sub 0.95/N-GaN composite-channel HEMTs

We report an Al/sub 0.3/Ga/sub 0.7/N-Al/sub 0.05/Ga/sub 0.95/N-GaN composite-channel HEMT with enhanced linearity. By engineering the channel region, i.e., inserting a 6-nm-thick AlGaN layer with 5% Al composition in the channel region, a composite-channel HEMT was demonstrated. Transconductance and cutoff frequencies of a 1 /spl times/100 /spl mu/m HEMT are kept near their peak values throughout the low- and high-current operating levels, a desirable feature for linear power amplifiers. The composite-channel HEMT exhibits a peak transconductance of 150 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 12 GHz and a peak power gain cutoff frequency (f/sub max/) of 30 GHz. For devices grown on sapphire substrate, maximum power density of 3.38 W/mm, power-added efficiency of 45% are obtained at 2 GHz. The output third-order intercept point (OIP3) is 33.2 dBm from two-tone measurement at 2 GHz.     

Ultrathin stacked Si/sub 3/N/sub 4//SiO/sub 2/ gate dielectrics prepared by rapid thermal processing

Ultrathin (58 AA equivalent oxide thickness) stacked Si/sub 3/N/sub 4//SiO/sub 2/ (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in O/sub 2/ and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO/sub 2/ and low-field breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flat-band voltage instability of MNOS devices was minimised, but the low-defect property was still preserved.<>     

Diamond FET using high-quality polycrystalline diamond with f/sub T/ of 45 GHz and f/sub max/ of 120 GHz

Using high-quality polycrystalline chemical-vapor-deposited diamond films with large grains (/spl sim/100 /spl mu/m), field effect transistors (FETs) with gate lengths of 0.1 /spl mu/m were fabricated. From the RF characteristics, the maximum transition frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were /spl sim/ 45 and /spl sim/ 120 GHz, respectively. The f/sub T/ and f/sub max/ values are much higher than the highest values for single-crystalline diamond FETs. The dc characteristics of the FET showed a drain-current density I/sub DS/ of 550 mA/mm at gate-source voltage V/sub GS/ of -3.5 V and a maximum transconductance g/sub m/ of 143 mS/mm at drain voltage V/sub DS/ of -8 V. These results indicate that the high-quality polycrystalline diamond film, whose maximum size is 4 in at present, is a most promising substrate for diamond electronic devices.     

High bandwidth and low-leakage current InP-In/sub 0.53/Ga/sub 0.47/As-InP DBHTs on GaAs substrates

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on GaAs substrates. A 284-GHz power-gain cutoff frequency f/sub max/ and a 216-GHz current-gain cutoff frequency f/sub /spl tau// were obtained, presently the highest reported values for metamorphic HBTs. The breakdown voltage BV/sub CEO/ was >5 V while the dc current gain /spl beta/ was 21. High thermal conductivity InP metamorphic buffer layers were employed in order to minimize the device thermal resistance.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

High-temperature thermal stability performance in /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As metamorphic HEMT

We report, to our knowledge, the best high-temperature characteristics and thermal stability of a novel /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As--GaAs metamorphic high-electron mobility transistor. High-temperature device characteristics, including extrinsic transconductance (g/sub m/), drain saturation current density (I/sub DSS/), on/off-state breakdown voltages (BV/sub on//BV/sub GD/), turn-on voltage (V/sub on/), and the gate-voltage swing have been extensively investigated for the gate dimensions of 0.65/spl times/200 /spl mu/m/sup 2/. The cutoff frequency (f/sub T/) and maximum oscillation frequency (f/sub max/), at 300 K, are 55.4 and 77.5 GHz at V/sub DS/=2 V, respectively. Moreover, the distinguished positive thermal threshold coefficient (/spl part/V/sub th///spl part/T) is superiorly as low as to 0.45 mV/K.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

GaN MOS device using SiO/sub 2/-Ga/sub 2/O/sub 3/ insulator grown by photoelectrochemical oxidation method

We report on a SiO/sub 2/-Ga/sub 2/O/sub 3/ gate insulator stack directly grown on n-type GaN by the photoelectrochemical oxidation method. The resultant MOS devices are fabricated using standard photolithography and liftoff techniques. The effect of annealing temperature on the SiO/sub 2/-Ga/sub 2/O/sub 3//n-type GaN MOS devices is investigated. The properties of high breakdown field, low gate leakage current, and low interface state density are investigated for the MOS devices.     

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.     

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

Novel design method for all-optical ultrafast gate switches using cascaded second-order nonlinear effect in quasi-phase matched LiNbO/sub 3/ devices

The authors propose a novel method of designing all-optical ultrafast gate switches that employ the cascade of the second harmonic generation and difference frequency mixing in quasi-phase matched LiNbO/sub 3/ devices. In this design method, the device length is maximized under the condition that crosstalk of the switch is maintained below a certain allowable value at a given bit rate. Following the design method, the authors find that the switching efficiency can significantly be enhanced by compensation for the walkoff between the fundamental and second harmonic pulses.