基于数据仓库技术决策支持系统模式的研究

基于目前大多数决策支持系统是单纯地基于C／S模式或B／S模式的情况下，在研究数据仓库的特点、组成及其实现的基础上，对C／S模式与B／S模式的决策支持系统进行了深入研究，提出了将C／S模式与B／S模式相结合的基于数据仓库决策支持系统模式。这种模式会增强决策支持系统的决策能力。     

基于B/S的汽车管理信息系统的设计与实现

针对当前汽车服务行业信息化管理的现状，在对C／S模式和B／S模式分析比较的基础上，提出了汽车服务行业的基于B／S模式的管理信息系统，并说明了其实现原理和关键技术。对B／S模式下的图形报表难点问题也给出了具体的实现方法。     

基于C/S模式和B/S模式结合的ZZGL系统开发方案

在企业管理信息系统开发中，单一的Client／Server(C／S)两层模式和Browser／Server(B／S)三层模式已经不能满足信息需求的快速发展，本文通过比较管理信息系统开发模式C／S和B／S模式的优缺点，提出以C／S和B／S模式相结合的系统开发思想，并作为实际开发的“武汉重型铸饭厂管理信息系统”(ZZGL系统)的设计实现方案。     

蓬于B／S模式的电力实时信息管理系统

论文首先对C／S模式和B／S模式进行了介绍,并分析了各自的优点。然后,结合公司的实际需求,提出了一种基于B／S模式的电力实时信息管理系统结构,并主要从系统的总体结构和系统的应用功能两个方面对该实时信息管理系统进行了阐述。     

C/S与B/S结合模式教学信息管理系统的规划与设计

分析了广泛应用于教学信息管理系统的客户机／服务器以及浏览器／服务器这两种模式各自的优点和不足，提出了两者相结合的信息管理系统结构模式，介绍了其中数据库的设计及C／S与B／S相结合综合模式的实所采用的技术。     

基于B／S和C／S混合架构的远程监控系统的设计

分析了B／S和C／S模式的优缺点,提出了一种基于B／S和C／S混合架构的远程监控系统设计方案,并以某系统的远程监控为例,对系统实现进行论述,为今后远程监控系统的优化提供了一定的参考。     

基于混合模式的MIS系统的分析与设计

对基于两层结构的C／S模式管理信息系统和基于三层结构的B／W／S模式管理信息系统进行比较。分析两种模式的特点、结构和应用范围，讨论了基于两者混合模式的MIS系统的可行性及其实现方式，并给出高校信息管理系统的分析与设计作为具体的设计实例。     

基于电子商务的中小物流企业共同配送信息系统探析

本文首先对共同配送信息系统及其网络架构作了基本介绍,描述了采用C／S和B／S混合结构模式的共同配送中心信息组织与集成框架;然后对中小物流企业共同配送信息系统业务流程进行了详细分析：最后提出了基于电子商务的中小物流企业共同配送信息系统的设计思路：采用微软公司的三层C／S与B／S混合结构模式,坚持开放性、标准化设计。     

高校学术成果管理系统的设计和实现

针对科研管理信息系统的子系统一学术成果管理系统进行了设计和实现。讨论了C／S模式和B／S模式混合模式使用的优越性，实现了学术成果管理信息系统的输入、修改、查询、统计分析和打印等多项功能，并利用OLE技术调用Excel实现了复杂表格的打印。     

B／S与C／S混合模式体系结构在河南省自学考试信息管理中的研究与应用

在对C／S、B／S模式结构进行分析比较的基础上,提出了基于C／S,B／S混合模式的体系架构,并对该结构的优点进行探讨,开发了河南省自学考试信息管理系统,该系统的各功能模块,真正实现了简单易学。功能完善。界面友好的特点。     

Asymptotic capacity of two-dimensional channels with checkerboard constraints

A checkerboard constraint is a bounded measurable set S/spl sub/R/sup 2/, containing the origin. A binary labeling of the Z/sup 2/ lattice satisfies the checkerboard constraint S if whenever t/spl isin/Z/sup 2/ is labeled 1, all of the other Z/sup 2/-lattice points in the translate t+S are labeled 0. Two-dimensional channels that only allow labelings of Z/sup 2/ satisfying checkerboard constraints are studied. Let A(S) be the area of S, and let A(S)/spl rarr//spl infin/ mean that S retains its shape but is inflated in size in the form /spl alpha/S, as /spl alpha//spl rarr//spl infin/. It is shown that for any open checkerboard constraint S, there exist positive reals K/sub 1/ and K/sub 2/ such that as A(S)/spl rarr//spl infin/, the channel capacity C/sub S/ decays to zero at least as fast as (K/sub 1/log/sub 2/A(S))/A(S) and at most as fast as (K/sub 2/log/sub 2/A(S))/A(S). It is also shown that if S is an open convex and symmetric checkerboard constraint, then as A(S)/spl rarr//spl infin/, the capacity decays exactly at the rate 4/spl delta/(S)(log/sub 2/A(S))/A(S), where /spl delta/(S) is the packing density of the set S. An implication is that the capacity of such checkerboard constrained channels is asymptotically determined only by the areas of the constraint and the smallest (possibly degenerate) hexagon that can be circumscribed about the constraint. In particular, this establishes that channels with square, diamond, or hexagonal checkerboard constraints all asymptotically have the same capacity, since /spl delta/(S)=1 for such constraints.     

Effect of interfacial oxide thickness on 1/f noise in polysilicon emitter BJTs

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.     

电子和中子辐照n型6H-SiC的光致发光谱

对用电子能量为1.7,0.5和0.4MeV的电子辐照和中子辐照后的n型6H-SiC样品进行低温光致发光研究.对于Ee≥0.5MeV电子辐照和中子辐照后的样品,首次发现了位于478.6/483.3/486.1n m的S1/S2/S3谱线.对样品进行热退火研究表明S1/S2/S3谱线在500℃下消失,而退火温度高于700℃时D1中心出现.考虑到产生C空位和Si空位所需的位移阈能以及热退火行为,说明S1/S2/S3为初级Si空位初级缺陷,而D1中心为二次缺陷.     

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

B/S与C/S体系结构的应用研究

通过分析B／S与C／S体系结构的优缺点，提出在管理信息系统中根据实际的功能需要，采用B／S与C／S相结合的体系结构。并阐述和分析了其在具体工程实际中的应用。     

A low-pass biquad derived filter realization

A biquad derived structure employing two Norton (current differencing) amplifiers is presented which requires the minimum number of components. Transfer characteristics of the form K/SUB 1//D(S) and K/SUB 2/(S+/spl omega//SUB n//Q)/D(S) with D(S)=S/SUP 2/+/spl omega//SUB n/S/Q+/spl omega//SUB n//SUP 2/ are realized. Biasing constraints are of major importance in the detailed realization and a typical circuit design is presented along with a discussion of its performance, which is compared with that of others.     

Energy-efficient skewed static logic with dual Vt: design and synthesis

In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S/sup 2/L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-/spl mu/m CMOS technology and verified that S/sup 2/L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S/sup 2/L is developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.     

物流管理系统的B/S结构实现

主要介绍了利用互联网资源而兴起的物流系统，以及目前较流行的B／S结构的特点和与C／S的比较；分析了构建一个B／S结构的物流管理系统的主要流程及主要功能模块；进一步说明使用B／S结构构建物流管理系统的主要优势。     

全差分BiCMOS采样/保持电路仿真设计

在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。