Low-voltage CMOS adjustable current mirror

A novel scheme for an adjustable low-voltage CMOS current mirror is introduced. The proposed current mirror provides continuous gain adjustment, while it simultaneously features the attractive characteristic of low-voltage operation. The behaviour of the proposed topology has been experimentally verified through a first-order lowpass filter fabricated in AMS 0.35 μm CMOS technology.     

Tunable linear CMOS current mirror

Based on triode MOSFETs as tunable devices, a tunable linear current mirror is proposed, whose current gain is tunable over a wide range. Simulations show that, total harmonic distortion on the output current is within 2% for a tuning range of almost five octaves. Although the structure is in the form of an active-input current mirror, keeping the tuned MOSFETs in triode region significantly relaxes the stability problems of an active-input current mirror. This issue is revealed by theoretical analyses and further simulations are included for demonstration. An application example is also supplied.     

A wide dynamic range continuously adjustable CMOS current mirror

A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current     

Temperature-compensated linear BiCMOS transconductor

A BiCMOS circuit technique for realising temperature-compensated linear transconductors is described which uses two linear MOS transconductors and a bipolar translinear current gain cell. The theory of operation is presented and simulation results are used to verify theoretical predictions. The results show that the transconductance can be varied over three decades and its temperature coefficient is <200 ppm/°C     

BiCMOS current steering pipeline circuit technique

The authors provide a new circuit technique for pipelined high fan-in nFET trees; the circuit is based on a current mode sense and latch arrangement. The technique uses the bipolar devices present in a BiCMOS technology as both a sensitive current detector, and a low impedance driver. The logic functionality is realised by embedding complex nMOS transistor trees inside nFET latches, and connecting slave TSPC pFET latches. The resulting configuration provides spatially and functionally dense implementations which are resistant to clock skew and charge sharing     

A BiCMOS low-power current mode gate

A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML     

BiCMOS current cell and switch for digital-to-analog converters

A BiCMOS current cell and current switch used in a current steering DAC are proposed. The BiCMOS self-calibrated current cell offers higher output resistance and smaller minimum voltage and shows up to a factor of 2 improvement in accuracy in simulations. The BiCMOS current switch has no base current error and achieves close to a factor of 2 improvement in simulated switching speed when compared to a MOS switch     

High-swing cascode MOS current mirror

A high-swing cascode triode-region MOS current mirror, basically comprising a triode-region translinear loop, is proposed. A translinear analysis and measurement results are presented     

High speed BiCMOS current mode differential track-and-hold circuit

A new principle for a high speed BiCMOS differential track-and-hold circuit based on current mode processing is presented, and simulation results are given. The main characteristics are an acquisition time of 5.5 ns for 8 bit precision and a small-signal bandwidth of 1 GHz     

High-speed active-input cascode current mirror

A high-speed active-input cascode current mirror is presented. The proposed configuration combines a high output impedance with the high-frequency performance of a source- or emitter-driven active-input topology. Simulation results in a 0.35 /spl mu/m SiGe BiCMOS are presented to demonstrate the validation of the proposed current mirror. A much higher (about 30 to 40 times) output impedance is achieved, with no degradation in the high-frequency behaviour compared to conventional emitter-driven active-input current mirrors, without increasing the power consumption. The proposed configuration can be applied to both bipolar and CMOS technology.     

基于电流镜的电流型PUF电路设计

通过对物理不可克隆函数(Physical Unclonable Functions,PUF)电路和电流镜的研究,提出一种基于电流镜的电流型PUF电路设计方案。该方案首先利用多路电流镜产生随机电流,然后使用电流型敏感放大器比较两路电流的大小,最后产生随机的输出响应。在SMIC 65nm工艺下,利用全定制方法设计PUF电路,在最小尺寸下PUF单元的版图面积为2.59μm×1.51μm。通过Spectre软件,在不同电压、温度等工作环境下进行Monte Carlo仿真验证,分析PUF电路的识别能力。实验结果表明所设计的PUF电路逻辑功能正确,且具有良好的随机性和稳定性,可广泛应用于密钥产生和设备认证等领域。     

Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.     

Si:SiGe MODFET current mirror

Measurements of the DC characteristics of a negative inverting, voltage-following current mirror are presented. The circuit design uses prototype n-depletion mode, modulation doped field effect transistors employing Si:SiGe heterojunction technology and is based on recently established circuit design techniques for GaAs MESFET technology. The results show a quasi-linear response with gate voltage swings (V_gs ) of ±0.5 V. Increases in the achievable range of V_gs are anticipated through changes in material growth and device processing, and also through enhancement of the circuit design     

A novel highly accurate current mirror

A novel complementary metal-oxide semiconductor (CMOS) current mirror that can work in weak and strong inversion is proposed. The mirror is capable of accurately copying current in the nano-ampere range. The proposed scheme eliminates the DC matching error caused by the difference between drain-to-source voltages of both the input and output transistors. The proposed circuit was verified using ORCAD simulator in 0.8 μm CMOS process technology. Simulation results confirm the functionality and accuracy of the circuit.     

A broadband highly linear BiCMOS mixer for direct conversion applications

A highly linear BiCMOS double balanced mixer for direct conversion applications is described and optimized. Based on the combination of active and resistive concepts, and modeled as a variable feedback amplifier, it achieves a high linearity and a good conversion gain. The performances achieved are; a conversion gain up to 12 dB, an output P/sub -1 dB/ of -5 dBm, and a high linearity, with an OIP3 of about +23 dBm and an OIP2 not less than +54 dBm, while requiring a local oscillator power no more than +4 dBm. As it covers a broadband RF spectrum, it can be used for receiving all communication networks located from 0.9 GHz until 2.2 GHz. When active, it drains 6 mA from 3.6 V.     

Effect of reverse base current on bipolar and BiCMOS circuits

A detailed study on the effect of reverse base current (RBC) on the switching behavior of bipolar BiCMOS circuits utilizing advanced high-performance bipolar transistors is presented. It is shown that as the collector doping N_c is increased to overcome the Kirk effect (base stretching) during the switching transient, the avalanche-generated reverse base current in the collector-base junction may cause problems for bipolar output devices switching out of saturation. A basic bipolar inverter and various BiCMOS driver circuits were simulated based on measured avalanche multiplication factors from advanced bipolar transistors with various collector doping N _c. In the case of the basic bipolar inverter, the reverse base current may prevent the switching device from being shut off completely during the on-to-off transition and a self-sustained state may result which reduces the output voltage swing. For the common-emitter (CE) BiCMOS driver, a similar self-sustained state may also occur with the added adverse effect of excessive leakage in standby. Design and scaling considerations are discussed     

CMOS current Schmitt trigger with fully adjustable hysteresis

A CMOS current Schmitt trigger whose hysteresis is independent of process parameters, transistor dimensions and power supplies is described. The hysteresis is determined by two currents and is adjustable over the range of the input current. The circuit function can be extended to a two-input current comparator with adjustable hysteresis.<>     

A Schmitt trigger with current mirror feedback

The circuit of a simple trigger with positive feedback via the current mirror (with gain) and the resistive divider is proposed. The circuit operation is described and the hysteresis voltage is obtained. The basic design limitations are introduced. Both versions (CMOS and bipolar) are considered.     

A 200-MHz IF BiCMOS signal component separator for linear LINCtransmitters

The linear amplification with nonlinear components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial signal processing function of LINC. It forms two constant-amplitude phase-modulated signal components from the input signal. Due to the nonlinear signal processing involved, digital signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 μm BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a π/4-shifted DQPSK modulated North American Digital Cellular (NADC) signal. This implies a high degree of linearity in the implemented LINC transmitter     

Compact implementation of high-performance CMOS current mirror

A high-performance compact current mirror implementation with very low input resistance, very high output resistance, high copying accuracy, low input and output voltage supply requirements and high bandwidth is proposed. The circuit characteristics are validated with simulations in 0.5 /spl mu/m CMOS technology and with experimental results.