基于InSb-In薄膜磁阻元件电流传感器的应用

介绍了一种用InSb-In共晶体薄膜磁阻元件制成的电流传感器(MRCS)。为了检测微弱电流,此种电流传感器利用同时改变两个InSb-In磁阻元件阻值的途径来实现这一目的,设计了一种能较大幅度增大其输出电压的信号处理电路。当处理电路的电压增益为50~10000倍、,待测的50Hz交流电流在50mA~12A时,输出电压在0.3~3.5V变化,并且两者之间有比较好的线性关系,标准偏差小于0.02,完全能满足工业上对电流的监测作用,从而保护因异常情况停止运转的马达。     

Discrete superconducting vortex flow transistors

We have fabricated an overdamped superconducting discrete vortex flow transistor (DVFT) which consists of an array of Josephson junctions coupled together in parallel. Measurements on this DVFT indicate a current gain of 1.2 when the control current is injected parallel to the array of junctions. We have developed a model that successfully predicts the performance of our low-T_c DVFT, including its current gain. When the current is injected parallel to the array, the gain is linear in the number of junctions and can be made much greater than 1. Except for the output voltage, the results of the DVFT are comparable to those of the present high-T_c devices     

Simulation and modeling-computer-aided, open-loop circuit analysis

An inverse circuit method is presented for performing computer-aided, open-loop circuit analysis. The analytical method consists of placing the circuit to be analyzed into the feedback loop of a high-gain differential current amplifier model. The gain of the resultant circuit is the inverse of the original gain. Also, the roles of the input and output are interchanged and the input to the original circuit can be determined as a function of its output. Both the output voltage and current are taken to be the closed-loop feedback voltage and current at the point where the loop is broken; thus, the output of the open loop is always properly loaded     

Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220×320 μm~2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.     

适合容性负载的高压大功率放大器

设计了一种适合压电陶瓷等容性负载的双极性可调高压大功率线性放大器,它由简单低廉的低压运算放大器、基于功率场效应管(MOSFET)的功率放大级组成主回路,通过电压负反馈构成闭环控制。对电路中各环节的特性进行了分析,并讨论了放大器的性能。该高压放大器在驱动等效电容为60nF的压电陶瓷时,单端到地输出电压为一600～ 600V,电压增益42dB,大信号带宽800Hz,小信号带宽7kHz,充放电电流可达200mA,静态电流可达1．4mA。实验与分析表明,高压直流放大器采用功率场效应管和电压闭环控制后,可拓展放大器通频带,提高放大器输出能力和长时间稳定性。     

A Differential CMOS Current-Mode Variable Gain Amplifier with Digital dB-Linear Gain Control

A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of the presented approach.     

A novel structure of the fully differential CMOS amplifier with symmetric active load

In this article, we propose a novel general structure of a linear symmetric fully differential voltage amplifier with a symmetric output. It is applicable to all sets of complementary component pairs such as BJT, JFET and MOSFET. We demonstrate the superiority of the proposed circuit in comparison with the state-of-the-art solutions. The characteristics are illustrated in both frequency and time domains, and a comparison is given between the proposed amplifier and the traditional differential amplifier with a current mirror as an active load for the same set of complementary components in CMOS equally sized W/L = 150/3 technology. The static voltage transfer characteristic of the proposed amplifier has an extremely small linearity error. The deviation from the linear characteristics is less than 0.018 mV for the amplitude of the output differential voltage of 1 Vpp. The common-mode gain by symmetric output is negligible because the proposed structure is fully symmetric. The simulation results demonstrate the efficiency of the proposed amplifier.     

60-GHz high power performance In/sub 0.35/Al/sub 0.65/As-In/sub 0-35/Ga/sub 0.65/As metamorphic HEMTs on GaAs

We report on a double-pulse doped, double recess In/sub 0.35/Al/sub 0.65/As-In/sub 0.35/Ga/sub 0.65/As metamorphic high electron mobility transistor (MHEMT) on GaAs substrate. This 0.15-/spl mu/m gate MHEMT exhibits excellent de characteristics, high current density of 750 mA/mm, extrinsic transconductance of 700 mS/mm. The on and off state breakdown are respectively of 5 and 13 V and defined It gate current density of 1 mA/mm. Power measurements at 60 GHz were performed on these devices. Biased between 2 and 5 V, they demonstrated a maximum output power of 390 mW/mm at 3.1 V of drain voltage with 2.8 dB power gain and a power added efficiency (PAE) of 18%. The output power at 1 dB gain compression is still of 300 mW/mm. Moreover, the linear power gain is of 5.2 dB. This is to our knowledge the best output power density of any MHEMT reported at this frequency.     

一种宽动态范围跨阻放大器的设计

针对光电探测器的光电流信号弱、变化范围大的特点,设计了一种全新的检测光电流信号的跨阻放大器(TIA)电路结构,其检测电流信号范围为1.6 μ上A～1.6 mA,动态电流检测范围达到60 dB.通过在电路内部设计出两个增益可调、增益段不同的TIA,分别处理光电流的小电流段(1.6～50 μA)和大电流段(50 μA～1.6 mA),增益可调范围为56～96 dBΩ;通过外置输出电压饱和检测信号,选择所需工作的TIA及其增益段.该电路采用0.18 μm标准CMOS工艺的PDK进行电路设计、版图设计和仿真验证等.测试结果表明:在检测电流为1.6 μA时,输出电压为95 mV;检测电流为1.6mA时,输出电压为915 mV,与仿真结果相一致.电路瞬态特性良好,上升时间为5～10 ns,3.3V电压下功耗小于2 mW,各指标满足设计要求.     

ISM频段中功率功率放大器

采用三指单胞的InGaP/GaAsHBT提取的大信号模型参数 ,设计出应用于ISM频段的三级AB类功率放大器 .通过对传统偏置网络的优化 ,消除了小信号下的增益压缩 .在 3 5V电压下 ,该放大器的最大线性输出功率为30dBm ,增益达到 2 9 1dB ,对应的功率附加效率为 4 3 4 % ,临近沟道抑制比达到 - 10 0dBc,而静态偏置电流很低 ,只有 10 9 7mA .     

用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2.4GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0.35μm CMOS工艺技术,在2V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3mA,输入三阶截距点达到20dBm,输出的信号幅度为87mV;下混频器消耗的电流为3.5mA,得到的转换增益是20dB,输入参考噪声电压是6.5nV/ Hz,输入三阶截距点为4.4dBm.     

ISM频段中功率功率放大器

采用三指单胞的InGaP/GaAs HBT提取的大信号模型参数,设计出应用于ISM频段的三级AB类功率放大器.通过对传统偏置网络的优化,消除了小信号下的增益压缩.在3.5V电压下,该放大器的最大线性输出功率为30dBm,增益达到29.1dB,对应的功率附加效率为43.4%,临近沟道抑制比达到-100dBc,而静态偏置电流很低,只有109.7mA.     

Precise Electronically Adjustable Oscillator Suitable for Quadrature Signal Generation Employing Active Elements with Current and Voltage Gain Control

A new oscillator suitable for quadrature and multiphase signal generation is introduced in this contribution. A novel active element, called the controlled gain-buffered current and voltage amplifier (CG-BCVA) with electronic possibilities for current and voltage gain adjustment is implemented together with a controlled gain-current follower differential output buffered amplifier (CG-CFDOBA) for linear adjustment of the oscillation frequency and precise control of the oscillation condition in order to ensure a stable level of generated voltages and sufficient total harmonic distortion. The parameters of the oscillator are directly controllable electronically. Simultaneous changes of two current gains allow linear adjusting of the oscillation frequency, and a controllable voltage gain is intended to control the oscillation condition. A detailed comparison of the proposed circuits with recently developed and discovered solutions employing the same type of electronic control is provided and shows the useful features of the proposed oscillator and utilized methods of electronic control. Behavioral models based on commercially available ICs have been used for experimental purposes. CMOS implementation of active elements was introduced and utilized for additional simulations and studies. Non-ideal analysis, Monte Carlo statistical evaluations of simulated models, and further analyses were performed for the exact determination of the expected results. Laboratory experiments confirmed the workability and estimated behavior of the proposed circuit as well.     

A Low-Supply-Voltage CMOS Sub-Bandgap Reference

A low-power (21 $muhbox{W}$ ) bandgap reference source that is operable from a nominal supply voltage of 1.4 V is described. The circuit provides an output voltage equal to the bandgap voltage having a low output resistance and allows resistive loading. It does not use resistors or operational amplifiers. Thus, the design is suitable for fabrication in any digital CMOS technology. The circuit uses a current conveyor and current mirrors to convert the proportional to absolute temperature voltage into a current using a MOSFET. The current is converted back to a voltage by using the functional inverse of the FET $v-i$ characteristics. This makes the voltage gain linear and temperature independent. The absence of back-gate bias is the reason for achieving the low supply voltage of operation. Simulation results using the transistor models for the 0.18-$mu$m TSMC process show that the voltage-variation over the temperature range 0 to 100 $^{circ} {hbox {C}}$ is $≪$1 mV.      

电流可线行调整的BiCMOS镜像恒流源电路

本文提议了两种新颖的电流可线行调整的BICMOS镜像恒流源电路，通过在控制环中引入一个直流电压源来调整镜像恒流源电路的电流增益。     

A high-temperature, high-voltage, fast response linear voltage regulator

This paper reports a high-temperature integrated linear voltage regulator implemented in a 0.8-??m BCD (bipolar, CMOS and DMOS)-on-silicon-on-insulator process. This step-down voltage regulator converts an unregulated high input DC voltage to a regulated nominal CMOS voltage (i.e. 5?V) for the low-side buffer (pre-driver) and other digital and analog building blocks of a high-temperature integrated gate driver circuit. An error amplifier inside the regulator has been designed using inversion coefficient methodology, and a temperature stable current reference has been used to bias the error amplifier. The linear regulator provides an output voltage of 5.3?V at room temperature and can supply a maximum load current of 200?mA. The linear voltage regulator integrated circuit has been tested at ambient temperatures from 25 to 200?°C with the input voltage varying from 10 to 30?V. A compensation method (pole swap) that extends the range of the system stability has been implemented and analyzed in detail. The simulated unity gain bandwidth can reach approximately 4?MHz when the load current is 200?mA and the measured transient response time is less than 150?nS when the load current is 50?mA and the ambient temperature is 200?°C.     

An on-chip 96.5% current efficiency CMOS linear regulator using aflexible control technique of output current

This paper proposes an on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current (FCOC). By the use of the FCOC technique, the proposed circuit realizes flexible output current drive according to the load current variation. Therefore, the proposed linear regulator ran supply stable output voltage using the FCOC technique. The linear regulator is fabricated by double-metal 1.2-μm CMOS technology. The number of transistors is 46 and the die size is 0.423 mm². The fabricated linear regulator achieves a fluctuation of output voltage less than 6.81 mV_p-p at a frequency of output current f(I_out) ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can achieve 96.5% current efficiency     

A GaAs Power MESFET Operating at 3.3V Drain Voltage for Digital Hand-Held Phone

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital hand-held phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using 0.8 μm design rule, showed a maximum drain current density of 330 mA/mm at V_gs = 0.5V and a gate-to-drain breakdown voltage of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.     

A Multicell Linear Power Amplifier for Driving Piezoelectric Loads

A multicell amplifier is developed by connecting floating signal modules in series to drive piezoelectric devices. The amplifier generates a high voltage gain by summing the individual module gains. The bandwidth equals that of a single module. The multicell amplifier provides a means of achieving high power and can divide the total power dissipation among the modules, because each module delivers the same output voltage and current. A prototype circuit that consists of six floating signal modules exhibits precise linear operation over a wide range of input frequencies and capacitive loads. The circuit provides a plusmn 200-V output swing with a corner frequency of around 100 kHz at a driving capacitive load of 0.1 muF. The slew rate is as high as 115 V/mus, and the maximum output current is plusmn2.6 A. The practicality and performance of the presented modular implementation concepts were verified by the close match between the simulated and experimental results.     

Three-section semiconductor optical amplifier for monitoring ofoptical gain

A 1.5-μm multiquantum well amplifier divided into three sections with short contacts at the input and output facets is described. A simple derivation shows that the amplifier optical gain is proportional to the ratio of voltage changes at the facet contacts induced by the optical signal. Measurements of optical gain and contact voltage as a function of amplifier bias current are in good agreement with the theory