Tunnel-diode-transistor binary counter

The principle of operation and the performance of a binary counter using a tunnel diode in the collector-emitter lead of a transistor is investigated. Simplified design procedure and lesser component configuration are the special features of the proposed hybrid binary.     

Complementary-MOS low-power low-voltage integrated binary counter

An integrated complementary MOS-transistor binary counter stage, particularly suited to low-power low-voltage applications, has been realized in monolithic form. The topology of the circuit allows one to group together all p-channel MOSTs and all n-channel MOSTs within two distinct surface areas. This feature results in an appreciable reduction of the surface necessary for a given circuit function. Dynamic current consumption is about 10 nA per kHz at a supply voltage of 1.35 volts. The complementary type of substrate is obtained by etching and epitaxially refilling wells in the original substrate material. Technological problems which had to be solved in order to achieve low-power low-voltage operation in complementary integrated MOS circuits will be discussed.     

基于电路三要素理论的五值计数器研究

本文提出六值代数,建立五值电路三要素理论(信号、网络和负载理论),作为定量研究五值电路的数学工具。在此基础上,首先用δ展开法由五值电路功能直接推出具有复位功能的五值反相器和动态D触发器的元件级结构。然后,对五值计数器进行研究,将其划分为五种类型,并设计出电路结构简单的具有复位功能的五值移位计数器。计算机模拟验证了上述理论和电路的正确性。     

A 60-GHz NbN single-flux quantum counter circuit

A Josephson binary counter using single-flux quanta transitions of DC SQUIDs (superconducting quantum interference devices) has been fabricated using an eight-level NbN-based process. High-speed binary division has been demonstrated at 4.2 K, with single-cell counting observed at 60 GHz using the Josephson voltage-to-frequency relationship. Count rate was primarily limited by conservative process and design rules. The counter was designed for operation at 4.2 K. At 8-10 K, the β_L of the SQUIDs would not allow operation, though the junction characteristics were good     

Tunnel diode full binary adder circuit

A simple full binary adder circuit employing a tunnel diode and a transistor is proposed. It has a well defined operation and is capable of operating at rates up to 200 MHz.     

基于TTL电路的倒数计数器设计及应用

介绍了基于TTL电路设计的倒数计数器，该电路结构简单，调试方便，时间设置范围广，无需单片机开发系统和编程，用途广，易于制作。     

Design of ternary counter based on adiabatic domino circuit

By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.     

Fast binary logarithm computing circuit for binary numbers less than one

A fast and expandable circuit for computing the approximate binary logarithm and antilogarithm of a fractional binary number is described. Illustration examples are included, and accuracy of the circuit is discussed.     

Multiplier less high-speed squaring circuit for binary numbers

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth’s algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.     

基于二叉树的CVSL电路优化方法

CVSL电路不同于互补CMOS逻辑那样具有固定的构成规则,对于复杂逻辑,若不对电路进行优化,则电路速度、版图面积、功耗等性能指标均会受到影响。因此用一种方法有规律的来完成CVSL电路结构的设计显得十分重要,传统的卡诺图化简法步骤过多,结构不够直观,针对这一缺陷,提出了用二叉树代替传统的卡诺图法的设计思路,从而使CVSL电路结构得到优化。分析结果表明,二叉树优化法较卡诺图法可使电路获得了更加高效的设计结果。     

倒计数器测频电路的设计与实现

将雷达发射脉冲信号下变频并整形形成中频TTL(晶体管-晶体管逻辑电路)方波信号,根据倒计数器测频的原理,选择二进制同步计数器74LS161三片级联后对该信号进行计数,取信号的300个脉冲形成计数区间,在此区间内用三片级联的74F161对100 MHz的标准方波进行计数,随后将计数结果送入单片机,由单片机计算出当前的中频频率,在控制DDS本振频率合成器对本振输出进行调整,保证中频信号频率稳定在规定范围内,由此构成数字式的雷达自动频率控制系统.     

New binary codes

In this paper constructions are given for combining two, three, or four codes to obtain new codes. The Andryanov-Saskovets construction is generalized. It is shown that the Preparata double-error-correcting codes may be extended by about (block length)^{1/2}symbols, of which only one is a check symbol, and thate-error-correcting BCH codes may sometimes be extended by (block !ength)^{1/e}symbols, of which only one is a check symbol. Several new families of linear and nonlinear double-error-correcting codes are obtained. Finally, an infinite family of linear codes is given withd/n = frac{1}{3}, the first three being the(24,2^12, 8)Golay code, a(48,2^15, 16)code, and a(96,2^18, 32)code. Most of the codes given have more codewords than any comparable code previously known to us.     

New binary codes

We report on the construction of many binary linear codes improving the tables of the best known codes. We obtained our results by applying the following known constructions: shortening and puncturing codes by analyzing their duals; and transferring a [64,8,43] code over GF(4) into a binary code and applying various constructions to the resulting code     

New active-gyrator circuit

Ideal passive gyrators can be made using two operational amplifiers, and it has been proved that they cannot be made with only one amplifier. However, this latter proof led to the discovery that an ideal active gyrator can be made with only one amplifier. A circuit for doing this is presented here, and its behaviour when used in an inductance-simulating mode is analysed.     

New frequency-discriminator circuit

This new frequency-discriminator circuit uses a single LC tuned circuit; setting up is minimal and the centre frequency is easily adjustable. The characteristic is linear for input-frequency deviations of 1% or more The maximum carrier frequency is limited to a few megacycles per second by the transistor feedback-amplifier techniques used.     

基于扭环形计数器设计交通信号灯自动控制电路

为了提高学生的数字电子技术综合实践能力,设计交通信号灯自动控制数字电子技术实验电路。选用D触发器和555定时器作为主要器件,利用组合逻辑电路、时序逻辑电路和555定时器等方面的数字电路理论,将扭环形计数器应用到十字路口交通信号灯自动控制电路中,并利用Multisim作为设计工具进行仿真。     

New binary Euclidean algorithms

Two new binary Euclidean algorithms to calculate the greatest common divisor are given. An exhaustive search for all odd integers of moderate length shows that these algorithms use fewer iterations on the average than that the two presently known algorithms     

Ring-structured adaptable logic circuit for the classification of binary vectors

A ring structure made of 8 bit random-access memory (r.a.m.) elements is described. The r.a.m.s. are used as variable-function logic devices. Several results are presented relating the stored functions to the overall system function. These include the detection of unique, isolated `1? bits (uniqueness) and unique strings of `1? bits (connectedness) in a binary vector.     

A compact high-speed (31,5) parallel counter circuit based oncapacitive threshold-logic gates

A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The counter circuit is implemented using conventional 1.2 μm double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm². Extensive post-layout simulations indicate that the circuit has a typical input-to-output propagation delay of less than 3 ns, and the test circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding circuits     

New phase-sensitive rectifier circuit

The principle of operation of a recent phase-sensitive rectifier demodulator circuit is discussed. The incorporation of this in a commercial lock-in amplifier has allowed the recovery of signals 70 dB below the noise level, while giving an output stability of better than 0·02% full scale per degree kelvin.