A 1.4-V 25-Mw 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process.     

一种10位高速Pipeline-SAR混合型ADC设计

基于180 nm CMOS工艺,设计了一种无残差放大的10位100 MS/s流水线与逐次逼近混合型ADC。采用两级流水线-逐次逼近混合型结构,第一级完成4位粗量化转换,第二级完成6位细量化转换。为了降低整体电路功耗,采用单调式电容控制切换方式,两级之间残差电压采用采样开关电荷共享方式实现。采用异步时序控制逻辑,进一步提升了能量利用率和转换速度。后仿真结果表明,在100 MS/s奈奎斯特采样率下,有效位数为9.39 bit,信噪失真比为58.34 dB,1.8 V电源电压下整体功耗为5.9 mW。     

一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm².     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

This paper presents a pipelined analog to digital converter (ADC) with reconfigurable resolution and sampling rate for biomedical applications. Significant power saving is achieved by turning off the sample-and-hold stage and the first two pipeline stages of the ADC instead of turning off the last two stages. The reconfiguration scheme allows having three modes of operation with variable resolutions and sampling rates. Reconfigurable operational transconductance amplifiers and an interference elimination technique have been employed to optimize power-speed-accuracy performance in biomedical instrumentation. The proposed ADC exhibits a 56.9 dB SNDR with 35.4 mW power consumption in 10-bit, 40 MS/s mode and 49.2 dB SNDR with only 7.9 mW power consumption in 8-bit, 2.5 MS/s mode. The area of the core layout is 1.9 mm² in a 0.35 μm bulk-CMOS process.     

一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.     

一个低电压低功耗10位30MS/s流水线A/D转换器

实现了一个10位精度,30MS/s,1.2V电源电压流水线A/D转换器,通过采用运放共享技术和动态比较器,大大降低了电路的功耗。为了在低电源电压下获得较大的摆幅,设计了一个采用新颖频率补偿方法的两级运放,并深入分析了该运放的频率特性。同时还采用了一个新的偏置电路给运放提供稳定且精确的偏置。在30MHz采样时钟,0.5MHz输入信号下测试,可以得到8.1bit有效位的输出,当输入频率上升到60MHz(四倍奈奎斯特频率)时,仍然有7.9bit有效位。电路积分非线性的最大值为1.98LSB,微分非线性的最大值为0.7LSB。电路采用0.13μmCMOS工艺流片验证,芯片面积为1.12mm2,功耗仅为14.4mW。     

一种流水线型ADC的时序改进技术研究

对一种流水线型模数转换器(ADC)的时序电路进行了改进研究。改进时序延长了余量增益单元MDAC部分加减保持相位的时长,可以在不增加功耗与面积的情况下,将一种10位流水线型ADC在20 MS/s采样率下的有效位(ENOB)从9.3位提高到9.8位,量化精度提高了5%;将该ADC有效位不低于9.3位的最高采样率从21 MS/s提高到29 MS/s,转换速度提高了35%。ADC的采样频率越高,改进时序带来的效果越显著。该项技术特别适用于高速高精度流水线型ADC,也为其他结构ADC的高速高精度设计提供思路。     

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.     

A 1 Gsps and 840 µW fully dynamic asynchronous pipelined binary search ADC

In this paper a very low power asynchronous 5-bit ADC in CMOS 45 nm process technology is described which combines the pipeline and binary search architectures. Due to utilization of dynamic non-linear amplifier, power consumption of the converter is very low. The ADC circuit uses digital calibration technique to update the reference voltages of the comparators. The power consumption of ADC is 840 µW, and the ENOB is 4.05 at 1 Gsps with input signal at the Nyquist rate. At sampling rate of 10 0Msps, the power consumption is reduced to 89 µW and the ENOB is equal to 4.6 again at the Nyquist rate.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

一种基于新型低功耗开关策略的10 bit 120 MS/s SAR ADC

设计了一种10 bit 120 MS/s高速低功耗逐次逼近模数转换器(SAR ADC)。针对功耗占比最大的CDAC模块,基于电容分裂技术并结合C-2C结构,提出了一种输出共模保持不变的双电平高能效开关控制策略;在降低CDAC开关功耗的同时,摆脱了CDAC开关过程中对中间共模电平的依赖,使得该结构适用于低电压工艺。在速度提升方面,控制逻辑使用异步逻辑进行加速;比较器采用一种全动态高速结构,在保证精度的前提下其工作频率达到3 GHz; CDAC中插入冗余位,以降低高位电容对充电时间的要求。所设计的SAR ADC使用40 nm CMOS工艺实现,采用1.1 V低电压供电。在不同工艺角下进行性能仿真,结果显示,在120 MHz采样率下,有效位数为9.86 bit,无杂散动态范围为72 dB,功耗为2.1 mW,优值为18.9 fJ/(conv·step)。     

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.      

A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter(ADC) is presented.This ADC with single track-and-hold(T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits(ENOB) and 47.84 dB of the spurious free dynamic range(SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate;it achieves 5.48 bit of ENOB a...     

A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.     

一种低功耗14位10MS/s流水线A/D转换器

基于0.6μm BiCMOS工艺,设计了一个低功耗14位10MS/s流水线A/D转换器.采用了去除前端采样保持电路、共享相邻级间的运放、逐级递减和设计高性能低功耗运算放大器等一系列低功耗技术来降低ADC的功耗.为了减小前端采样保持电路去除后引入的孔径误差,采用一种简单的RC时间常数匹配方法.仿真结果表明,当采样频率为10MHz,输入信号为102.5kHz,电源电压为5V时,ADC的信噪失真比(SNDR)、无杂散谐波范围(SFDR)、有效位数(ENOB)和功耗分别为80.17dB、87.94dB、13.02位和55mW.