40-GHz transimpedance amplifier with differential outputs using InP-InGaAs heterojunction bipolar transistors

High-gain and high-bandwidth transimpedance amplifiers (TIAs) are required for fiber-optic receiver modules. This paper reports on the design, fabrication, and characterization of a 40-Gb/s TIA for SONET/SDH STS-768/STM-256 applications based on an InP-InGaAs single heterojunction bipolar transistor (SHBT) process developed at Vitesse Semiconductor Corporation (Vitesse Indium Phosphide Release 1 or VIP-1). This amplifier consists of a single-ended input transimpedance pre-amplifier and a differential output post-amplifier. The measured differential transimpedance is 1800 /spl Omega/ with -3-dB bandwidth greater than 40 GHz. The high gain of this circuit eliminates the need for a standalone limiting amplifier between the conventional transimpedance pre-amplifier and the demultiplexer in short-reach applications.     

Noise analysis and optimization of VCII-based SiPM interface circuit

Analog Integrated Circuits and Signal Processing - Recently, second generation voltage conveyor (VCII)-based transimpedance amplifiers (TIAs) have begun to find their way in different applications,...     

Design of active transimpedance band-pass filters with different Q values

Transimpedance filter is a filter which realises a transimpedance transfer function. In this article, the design methods for the transimpedance band-pass filter are presented. The circuit topologies and parameter calculation formulas of three bi-quadratic transimpedance band-pass filter topologies with low-, medium- and high-Q values are proposed, respectively. A high-order transimpedance filter can be obtained by realising a bi-quadratic transimpedance filter first and then cascaded with voltage-mode bi-quads. A high-order transimpedance filter design example is given; the simulation and the measured results verify the effectiveness of the proposed transimpedance filter design method.     

Design of active transimpedance band-pass filters with different Q values

Transimpedance filter is a filter which realises a transimpedance transfer function. In this paper, the design methods for transimpedance band-pass filter are presented. The circuit topologies and parameter calculation formulas of three bi-quadratic transimpedance band-pass filter topologies with LQ, MQ and HQ are proposed respectively. High order transimpedance filter can be obtained by realising a bi-quadratic transimpedance filter first and then cascaded with voltage mode bi-quads. A high order transimpedance filter design example is given, the simulation and the measured results verify the effectiveness of the proposed transimpedance filter design method.     

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz     

Shunt bootstrapping technique to improve bandwidth oftransimpedance amplifiers

The input capacitance of transimpedance amplifiers can limit their response time. One novel technique based on a shunt bootstrap method is shown to be of advantage to op-amp based circuits with a high transimpedance gain     

Low-noise, high-gain Si-bipolar preamplifiers for 10 Gb/soptical-fiber links-design and realization

Design principles and circuit configurations of Si-bipolar transimpedance preamplifiers for 10 Gb/s optical-fiber links are discussed. The target specifications of the amplifier are near the limit achievable by the available technology. Therefore, the different amplifier stages had to be carefully optimized with respect to both flat magnitude and constant group delay of the total transimpedance up to about 7.5 GHz. Two different versions of preamplifiers were fabricated in an advanced production technology (f_T≈23 GHz). High transimpedance (710 Ω) and low equivalent input noise current density (averaged: ≈9 pA/√(Hz)) were achieved     

Design of broadband transimpedance amplifier for optical communication systems

This paper describes the design and analysis of broadband transimpedance amplifiers (TIAs) based on Regulated Cascode (RGC) configuration. The focus is to deal with bandwidth restriction occurring in optical receivers coming from TIA input parasitic capacitances. Despite the conventional method for broadband RGC TIA design that a ladder matching network is employed to isolate the input capacitance of TIA and the photodiode capacitance, the proposed TIA eliminates the effects of these parasitic components by absorbing them in a T-matching network. The conventional broadband RGC TIA is analyzed and the disadvantages of the ladder matching network is demonstrated in a TIA design example. The proposed RGC TIA is simulated on 0.18-μm standard RF CMOS process. The simulation results presented show that the Gain-Bandwidth product (GBW) is extended by a larger factor compared to that of the conventional broadband RGC TIA while the biasing conditions and the value of the photodiode capacitance are considered the same.     

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak$f_T$(approx. 0.3$hbox mA/muhbox m$), peak$f_ MAX$(approx. 0.2$hbox mA/muhbox m$), and optimum noise figure$ NF_ MIN$(approx. 0.15$hbox mA/muhbox m$) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40–80 Gb/s wireline transceivers.     

Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications

On the basis of a realized 12$,times,$ 10 Gb/s card-to-card optical link demonstrator, the capabilities of a polymer-waveguide-based board-level optical interconnect technology are presented. The conception and realization of the modular building blocks required for this board-level optical interconnect technology are described in detail. In particular, we report on the fabrication and characterization of board-integrated optical low-loss polymer waveguides that are compatible with printed circuit board (PCB) manufacturing processes. We also explain our fully passive alignment technique, superseding time-consuming active positioning of components and connectors. To realize optical transceiver modules comprising vertical cavity surface emitting laser (VCSEL) arrays with laser drivers and photodetector arrays with transimpedance amplifiers (TIAs), a mass-production concept based on wafer-level processing has been elaborated and successfully implemented.      

Design of a low EMI susceptibility CMOS transimpedance operational amplifier

In this work we analyze the effects of electromagnetic-induced interferences conveyed at the input of a transimpedance CMOS operational amplifier. In particular, it will be highlighted that transimpedance amplifiers natural exhibit a lower EMI susceptibility compared to common voltage-feedback opamps. Moreover, it will be shown through simulations that a careful circuit design can lead to opamps with a practically vanishing EMI susceptibility.     

一种宽输入动态范围跨阻放大器的设计

利用对数放大的增益可变性特点,设计出基于对数放大的跨阻放大器,克服了采用传统AGC调整跨阻的复杂性和低可靠性;同时,避免了采用肖特基二极管箝位方法的工艺局限性,有效扩展了跨阻放大器的输入动态范围。在详细分析跨阻动态特性及温度特性的基础上,分析了电路噪声性能,并进行了仿真验证。试验样片的测试结果进一步证明所提出的方法是有效的。     

Using High Frequency Operational Amplifiers for Low Noise Design

In this paper we present a comprehensive noise and stability analysis of both the current feedback and the voltage feedback op-amp when connected as transimpedance amplifiers with capacitive current sources. It is generally assumed that the current feedback op-amp is noisier than the voltage feedback op-amp; we show how external component values play an important role in determining the total equivalent input noise current spectral density and show that the voltage feedback op-amp may, in certain cases, be noisier than the current feedback op-amp. Both amplifier types are compared in terms of stability, noise and bandwidth; we find that the current feedback op-amp is particularly suited for operation as a transimpedance amplifier. Theoretical analysis is confirmed by simulations of equivalent circuits of the current feedback op-amp and the voltage feedback op-amp, and simulations of the macro models of two high performance commercially available op-amps, namely the Elantec EL2260 current feedback op-amp and the Elantec EL2244 voltage feedback op-amp.     

一种带有改进的25%占空比本振产生电路的WCDMA/GSM高线性度接收机射频前端分析与设计

本文提出了一种满足WCDMA/GSM系统要求的全集成接收机射频前端。WCDMA模式下无需声表面波滤波器。为了提高包括IP3和IP2指标在内的线性度性能,射频前端包括电容减敏的多栅低噪声放大器、带有本文提出的IP2校准电路的电流模式无源混频器以及似Tow-Thomas结构的双二阶可重构跨阻放大器。本文提出了一种新的低功耗、低相噪、可产生四相25%占空比本振信号的多模分频器。同时,本文通过采用带有片上电阻的恒定gm偏置电路,减小工艺和温度对转换增益的影响。本文中的射频前端电路集成在一个0.13um CMOS工艺下实现的带有片上频率综合器的接收机中。测试结果显示,在这个高线性度射频前端的帮助下,对于所有的模式和频带,接收机可以获得-6dBm的IIP3和至少 60dBm的IIP2。     

Improvements to the standard theory for photoreceiver noise

The standard theory for photoreceiver noise unrealistically defines the system transfer function solely in terms of the input and output pulse shapes, based on the assumption that equalization is provided at the receiver output. Most photoreceivers reported in the literature, however, are only front ends and do not include equalizers, making direct application of the conventional noise expressions inappropriate. Even if equalization is provided, a signal-dependent definition of the transfer function will be accurate only under certain limited conditions. Furthermore, it is unrealistic to assume a given pulse shape at the input. In this paper we consider the effect of incorporating a more realistic transfer function into the conventional noise theory. We choose the transimpedance amplifier for our analysis due to its widespread popularity; however, our approach is general and can he applied to a broad class of photoreceivers. Since our transfer function is based on a physical circuit, our results can be used to estimate photoreceiver noise performance without making any assumptions on the input or output pulse shapes     

Design of transimpedance low-pass filters

The input of a transimpedance filter is a current signal, while its output is a voltage signal. In this article, a design method for a transimpedance filter is introduced. Also, the topologies and calculation methods of the parameters of three biquadratic transimpedance low-pass (LP) filter circuits are presented in detail, according to the value of Q which is low or medium or high. As for the high-order filter, it can be designed by transimpedance LP biquad section as first stage cascaded with voltage-mode LP filters. Finally, to verify the effectiveness of the design, a design example of a high-order transimpedance LP filter is given.     

Bandwidth enhancement of transimpedance amplifier by acapacitive-peaking design

Using a capacitive-peaking (C-peaking) technique to increase the bandwidth of a transimpedance amplifier has been proposed. An analytical model for determining the peaking capacitance in the Butterworth-type transimpedance amplifier design has been derived. Based on this approach, we can design a larger bandwidth of a transimpedance amplifier. The low-frequency transimpedance gain in our fabricated amplifier is 0,95 kΩ, and the 3 dB bandwidth of the transimpedance amplifier is enhanced from 1.1 to 2.3 GHz without sacrificing its low-frequency gain by this C-peaking technique     

A BJT translinear loop based optoelectronic integrated circuit with variable transimpedance for optical storage systems

A 0.35 μm SiGe BiCMOS optical receiver with voltage-controlled transimpedance is presented. A variable-gain current amplifier using a BJT translinear loop is applied. A transimpedance dynamic range of 1554 (63.8 dB) with the largest transimpedance of 2.84 MΩ, a bandwidth up to 379 MHz, and a transimpedance bandwidth product up to 168 TΩHz are achieved.     

A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/√Hz (rms), resulting in a very low detectable input current of 1 μ A with SNR=5.     

A RGC-based,low-power,CMOS transimpedance amplifier for 10Gb/s optical receivers

ABSTRACT

In this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µA_rms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage.