新型消费类电子光互连应用

介绍了光互连在新型消费类电子市场,如高清多媒体接口(HDMI)、通用串行总线(USB)、Display Port、专业音视频以及分体式电视领域的新应用。采用板上芯片封装(COB)方案为基础的新型消费类电子市场有源光缆(AOC),以其低成本生产技术、小体积、支持多路光通道集成的特点,自2018年以来迅速得到了市场的认可。进一步介绍了具有代表性的HDMI、USB以及分体式电视AOC的性能特性以及市场应用。认为大量的新型光电产品将会出现在消费类电子市场。     

全硅片上光互连用波导

较详细地分析了用于全硅片上光互连所用光波导（如多晶Si／SiO2、Si／SiO2、Si3N4/SiO2）需满足的基本条件、制作方法以及损耗机制,总结了目前的研究进展。     

硅通孔互连技术的开发与应用

随着三维叠层封装、MEMS封装、垂直集成传感器阵列以及台面MOS功率器件倒装焊技术的开发,硅通孔互连技术正在受到越来越广泛的重视和研究。文中叙述了几种硅通孔互连技术的制造方法,以及它们在三维封装、MEMS封装、高密度硅基板、垂直集成传感器阵列和台面MOS功率器件等方面的应用。最后,进一步阐述了硅通孔互连中几项关键技术的研究现状以及存在的挑战。     

硅通孔互连技术的开发与应用

随着三维叠层封装、MEMS封装、垂直集成传感器阵列以及台面MOS功率器件倒装焊技术的开发,硅通孔互连技术正在受到越来越广泛的重视和研究。本文叙述了几种硅通孔互连的制造方法,及其应用。最后,进一步阐述了硅通孔互连中几项关键技术的研究现状以及存在的挑战。     

On-Chip Optical Interconnect

We describe a cost-effective and low-power-consumption approach for on-chip optical interconnection. This approach includes an investigation into architectures, devices, and materials. We have proposed and fabricated a bonded structure of an Si-based optical layer on a large-scale integration (LSI) chip. The fabricated optical layer contains Si nanophotodiodes for optical detectors, which are coupled with SiON waveguides using surface-plasmon antennas. Optical signals were introduced to the optical layer and distributed to the Si nanophotodiodes. The output signals from the photodiodes were sent electrically to the transimpedance-amplifier circuitries in the LSI. The signals from the photodiodes triggered of the circuitries at 5 GHz. Since electrooptical modulators consume the most power in on-chip optical interconnect systems and require a large footprint, they are critical to establish on-chip optical interconnection. Two approaches are investigated: 1) an architecture using a fewer number of modulators and 2) high electrooptical coefficient materials.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Discrete Out-of-Plane Coupling Components for Printed Circuit Board-Level Optical Interconnections

We propose discrete out-of-plane coupling components as a versatile alternative to current approaches used to couple light in and out of the propagation plane in waveguide-based printed circuit board (PCB)-level optical interconnections. The out-of-plane couplers feature a 45deg micromirror and are fabricated using deep proton writing as a rapid prototyping technology. Their fabrication is compatible with replication techniques and shows all the potential of low-cost mass fabrication. In a first configuration, we use the component in a fiber-to-fiber coupling scheme. Coupling losses as small as 0.77 dB were achieved. In a second configuration, the out-of-plane coupler is plugged into a laser ablated cavity in optical waveguides integrated on a PCB. Here a total link loss between out-of-plane fiber and in-plane fiber of 3.00 dB was achieved when using it at the transmitter side and 5.69 dB when using it at the receiver side.     

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.     

薄膜高密度互连技术及其应用

高密度互连(HDI)基片在微电子集成技术中用来缩小尺寸、减轻重量和提高电气性能。薄膜技术是获得高密度互连的最佳技术。文章介绍了薄膜高密度互连技术的概念、特点、设计与工艺考虑,并指出其主要领域的应用情况。     

Self-Alignment of Optical Devices With Fiber for Low-Cost Optical Interconnect Modules

We propose a novel self-alignment process of optical devices with optical fiber. A vertical-cavity surface-emitting laser (VCSEL) was automatically coupled with a multimode fiber (MMF) through the surface tension of a liquid adhesive within 1.5 s. Misalignment between the center of the VCSEL and the fiber was measured to be 15 mum, which is acceptable for coupling the VCSEL with the MMF. High-speed pulse modulation of the self-aligned VCSEL up to 5 Gb/s, as well as at 1 Gb/s, was demonstrated. The average optical output power was as high as -5.9 dBm at 1 Gb/s.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

平行光纤互联技术：高性能和低能耗的结合

This paper analyzes the physical potential,computing performance benefit and power consumption of optical interconnects. Compared with electrical interconnections, optical ones show undoubted advantages based on physical factor analysis. At the same time, since the recent developments drive us to think about whether these optical interconnect technologies with higher bandwidth but higher cost are worthy to be deployed, the computing performance comparison is performed. To meet the increasing demand of large-scale parallel or multi-processor computing tasks, an analytic method to evaluate parallel computing performance of interconnect systems is proposed in this paper. Both bandwidth-limit model and full-bandwidth model are under our investigation. Speedup and efficiency are selected to represent the parallel performance of an interconnect system. Deploying the proposed models, we depict the performance gap between the optical and electrically interconnected systems. Another investigation on power consumption of commercial products showed that if the parallel interconnections are deployed, the unit power consumption will be reduced. Therefore, from the analysis of computing influence and power dissipation, we found that parallel optical interconnect is valuable combination of high performance and low energy consumption. Considering the possible data center under construction, huge power could be saved if parallel optical interconnects technologies are used.     

用光学分布时钟实现位同步的光互连网络设计

本文采用时分复用技术和高速交叉开关实现80Gbit/s的数据交换,通过引入光学分布时钟减小光信道之间进行切换时的链路重建时间。采用该位同步结构,可把机群系统网络互连通道切换时的链路重建时间由ms量级减小到us量级。数据包在网络中的通信延迟可减少2～个数量级。当时钟速率为1GHz,要求各结点的时钟相位差小于5%时钟周期时,对光纤长度误差要求为1cm。     

光纤技术的进展与应用

本文介绍了光纤的传输特性，简述了常规单模光纤和色散位移单模光纤的特点和应用，重点阐述了非零色散位移光纤的性能及光纤色散补偿技术，分析了各种光纤的应用条件。     

Mesh光互连网络集成模块研究

本文研究了一种新型的自由空间光互连Mesh网络集成模块。对Mesh光互连系统结构进行了设计,着重对系统模块中的光收发透镜阵列进行了光学设计,对两种不同设计方案进行了比较。结果表明,直接由透镜中心斜入射法能更好地满足Mesh互连网络的要求。     

Fully Embedded Board-Level Optical Interconnects From Waveguide Fabrication to Device Integration

This paper presents the latest progress toward fully embedded board-level optical interconnects in the aspect of waveguide fabrication and device integration. A one-step pattern transfer method is used to form a large cross-section multimode waveguide array with 45deg micromirrors by silicon hard molding method. Optimized by a novel spin-coating surface smoothing method for the master mold, the waveguide propagation loss is reduced to 0.09 dB/cm. The coupling efficiency of the metal-coated reflecting mirror, which is embedded in the thin-film waveguide, is simulated by an M² factor revised Gaussian beam method and is experimentally measured to be 85%. The active optoelectronic devices, vertical surface emitter lasers and p-i-n photodiodes, are integrated with the mirror-ended waveguide array and successfully demonstrate a 10 Gbps signal transmission over the embeddable optical layer.     

Impact of Microstructure Evolution and Isothermal Aging on Sn-Ag-Cu Solder Interconnect Board-Level High-G Mechanical Shock Performance and Crack Propagation

The root cause of shock-induced solder joint failures in the range of 800G to 1500G is investigated. Joint stability under various shock and strain level combinations and the impact of isothermal aging on board-level shock performance were analyzed. A test vehicle was developed to obtain various combinations of shock and strain levels in a single board. Using 17 mm × 17 mm body-sized ball grid array packages on a shock test board, isothermal aging was applied prior to shock testing to determine the impact of different interface microstructures. Results revealed clear indications of a correlation between shock and strain and a trend of isothermal-aging-induced degradation. A shift in the failure locations was observed based on the interface intermetallic microstructure, and some preliminary evidence for the influence of Sn grain orientation was identified. The interrelated effects of isothermal aging, locally experienced shock and strain levels, and Sn grain orientation on mechanical shock performance are discussed.     

纳米材料互连技术研究进展

纳米材料的互连技术是由纳米材料走向纳米器件的桥梁,是推动纳米材料大规模应用的必然基础之一。综述了近年来报道的可控的纳米材料焊接互连方法,包括焦耳热焊接、电子束焊接、光束焊接和原子力显微镜焊接,对其原理和特点进行了分析,并对此领域的发展趋势进行了展望。     

电气互联技术及其发展动态

介绍了电气互联技术的基本概念、组成和主要内容，并对电气互联技术与SMT的关系、电气互联技术研究和发展动态等问题进行了阐述。     

走向工业应用的离子辅助光学镀膜技术

介绍一种新型等离子体辅助镀膜技术,使用该技术可使高质量的光学镀膜大量生产。该技术核心是无栅等离子体源（ＧＩＳ）。ＧＩＳ可以产生大面积的均匀等离子体。直径大于１０００ｍｍ。等离子体离子流强度高达０．５ｍＡ／ｃｍ＾２,离子流能量２０－２００ｅＶ,并能激活反应气体Ｏ２及蒸发原子,用ＧＩＳ进行的等离子体离子辅助镀膜这一技术,现正用于生产高质量的光学薄膜。