Self-aligned control of threshold voltages in sub-0.2-μm MOSFETs

We propose a new method to control the threshold voltages (V_th) in sub-0.2 μm MOSFETs. The method suppresses V_th fluctuations caused by variations in the fabricated gate length. Our scheme is to change the concentration of the channel impurity according to the gate length by tilted ion implantation from two directions after the polysilicon gate formation. We show the feasibility of our process by two-dimensional (2-D) process and device simulations. Then we clarify that our scheme was realized in fabricated nMOSFETs. We also measured the V_th in numerous MOSFETs and show that our method can indeed suppress V_th fluctuations caused by variations in the fabricated gate length     

A transistor performance figure-of-merit including the effect ofgate resistance and its application to scaling to sub-0.25-μm CMOSlogic technologies

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-μm CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness     

Improvement of threshold voltage deviation in damascene metal gatetransistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (ΔV _th) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, ΔV_th of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (ΔV_th) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta₂O₅ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN     

Gate engineering for deep-submicron CMOS transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET' I-V characteristics, MOS capacitor quasi-static C-V curves, SIMS profiles, gate sheet resistance, and oxide Q_bd are compared for different nitrogen implant conditions. A nitrogen dose of 5×10¹⁵ cm^-2 is found to be the optimum choice at an implant energy of 40 keV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p⁺ gate p-MOSFET and n⁺ gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si_1-xGe_x is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active-dopant concentration near the gate/SiO₂ interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si_1-xGe_x is gate is compared with polysilicon gate in this study     

Impact of nitrogen (N14) implantation into polysilicongate on high-performance dual-gate CMOS transistors

The effect of nitrogen (N₁₄)implant into dual-doped polysilicon gates was investigated. The electrical characteristics of sub-0.25-μm dual-gate transistors (both p- and n-channel), MOS capacitor quasi-static C-V curve, SIMS profile, poly-Si gate R_s , and oxide Q_bd were compared at different nitrogen dose levels. A nitrogen dose of 5×10¹⁵ cm^-2 is the optimum choice at an implant energy of 40 KeV in terms of the overall performance of both p- and n-MOSFETs and the oxide Q_bd. The suppression of boron penetration is confirmed by the SIMS profiles to be attributed to the retardation effect in bulk polysilicon with the presence of nitrogen. High nitrogen dose (1×10¹⁶ cm^-2) results in poly depletion and increase of sheet resistance in both unsilicided and silicided p⁺ poly, degrading the transistor performance. Under optimum design, nitrogen implantation into poly-Si gate is effective in suppressing boron penetration without degrading performance of either p- or n-channel transistors     

The formation of Ti-polycide gate structure with high thermalstability using chemical-mechanical polishing (CMP) planarizationtechnology

A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi₂ gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region     

A metal/polysilicon damascene gate technology for RF power LDMOSFETs

This letter describes a metal/polysilicon damascene gate technology for RF power LDMOSFETs. We compare the performance of SOI LDMOSFETs with metal/polysilicon damascene gates to that of identical devices with n/sup +/ polysilicon gates. The gate sheet resistance of the metal/polysilicon gate was 0.2 /spl Omega//sq. This very low sheet resistance greatly improved f/sub max/ and peak PAE, especially for the wide gate fingers that are critical in RF power applications. With a 140 /spl mu/m gate finger width, f/sub max/ was improved from 5 GHz to 25 GHz, and peak PAE at 1.9 GHz was improved from 12% to 52%.     

High drive-current electrically induced body dynamic threshold SOIMOSFET (EIB-DTMOS) with large body effect and low threshold voltage

A novel electrically induced body dynamic threshold metal oxide semiconductor (EIB-DTMOS) is proposed where the body is electrically induced by substrate bias and its high performance is demonstrated by experiments and simulations. EIB-DTMOS achieves a large body effect and a low V_th at the same time. The upper limit of the supply voltage of the EIB-DTMOS is higher than that of a conventional DTMOS, because the forward biased p-n junction leakage current of the EIB-DTMOS is lower. Among several DTMOSs, the accumulation mode EIB-DTMOS shows the highest drive-current at fixed off-current due to a large V_th Shift (or large back gate capacitance) and a suppressed short channel effect     

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

Flexibly controllable threshold-voltage (V_th) asymmetric gate-oxide thickness (T_ox) four-terminal (4T) FinFETs with HfO₂ [equivalentoxidethickness(EOT)=1.4 nm] for the drive gate and HfO₂+thick SiO₂ (EOT=6.4-9.4 nm) for the V_th-control gate have been successfully fabricated by utilizing ion-bombardment-enhanced etching process. Owing to the slightly thick V_th-control gate oxide, the subthreshold slope (S) is significantly improved as compared to the symmetrically thin T_ox 4T-FinFETs. As a result, the asymmetric T_ox 4T-FinFETs gain higher I_on than that for the symmetrically thin T_ox 4T-FinFETs under the same I_off conditions     

Polysilicon encapsulated local oxidation

Polysilicon encapsulated local oxidation (PELOX) is proposed as an effective isolation technique that satisfied advanced device requirements without any difficult-to-control structures or processes. Simple modifications to a standard local oxidation of silicon (LOCOS) process flow minimize encroachment without introducing defects. These modifications include an HF dip after nitride patterning to form a cavity self-aligned to the nitride edge, reoxidation of exposed silicon, and polysilicon deposition to fill the cavity. Physical (scanning electron micrographs) and electrical (gate oxide quality, diode integrity, and W_eff) data which indicate that cavity reoxidation is critical to obtaining significant bird's beak reduction without defect introduction are presented     

Effect of dopant redistribution, segregation, and carrier trappingin As-implanted MOS gates

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi₂ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi₂. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior     

Threshold voltage uniformity and characterization of microwaveperformance for GaAs/AlGaAs high electron-mobility transistors grown onSi substrates

We report on DC and microwave characteristics for high electron-mobility transistors (HEMT's) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). Threshold voltage (V _th) distribution in a 3-in wafer shows standard deviation of V_th (σV_th) of 36 mV with V_th of -2.41 V for depletion mode HEMT's/Si and σV_th of 31 mV with V_th of 0.01 V for enhancement mode, respectively. The evaluation of V_th in a 1.95×1.9 mm² area shows high uniformity for as-grown HEMT's/Si with σV_th of 9 mV for V_th of -0.10 V, which is comparable to that for HEMT's/GaAs. Comparing the V_th distribution pattern in the area with that for annealed HEMT's/Si, it is indicated that the high uniformity of V_th is obtained irrelevant of a number of the dislocations existing in the GaAs/Si. From microwave characteristic evaluation for HEMT's with a middle-(10~50 Ω·cm) and a high-(2000~6000 Ω·cm) resistivity Si substrate using a new equivalent circuit model, it is demonstrated that HEMT's/Si have the disadvantage for parasitic capacitances and resistances originated not from the substrate resistivity but from a conductive layer at the Si-GaAs interface. The parasitic parameters, especially the capacitances, can be overcome by the reduction of electrode areas for bonding pads and by the insertion of a dielectric layer under the electrode, which bring high cut-off frequency (f_T) and maximum frequency of operation (f_max) of 24 GHz for a gate length of 0.8 (μm). These results indicate that HEMT's/Si are sufficiently applicable for IC's and discrete devices and have a potential to be substituted for HEMT's/GaAs     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

Gate oxide reliabilities in MOS (metal-oxide-semiconductor) structures with Ti-polycide gates

We have investigated the thermal degradation of gate oxide in metal-oxide-semiconductor (MOS) structures with Ti-polycide gates. We found that the Ti-diffusion into the underlying polysilicon and consequently to the gate oxide occurs upon thermal cycling processes, which results in the dielectric breakdown of the gate oxide. We also found that the Ti-diffusion is suppressed by the employment of the thin (about 5 nm) titanium nitride (TiN) diffusion barrier layer, which consequently improved the reliability characterisitics of gate oxide significantly.     

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

The inhomogeneity of Schottky-barrier (SB) height Phi_B is found to strongly affect the threshold voltage V_th of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness t_OX and SOI body thickness; the contribution of inhomogeneity to the V_th variation becomes less pronounced with smaller t_OX and/or larger t_si . Moreover, an enhanced V_th variation is observed for devices with dopant segregation used for reduction of the effective Phi_B . Furthermore, a multigate structure is found to help suppress the V_th variation by improving carrier injection through reduction of its sensitivity to the Phi_B inhomogeneity. A new method for extraction of Phi_B from room temperature transfer characteristics is also presented.     

Measurements and modeling of MOSFET I-V characteristics withpolysilicon depletion effect

The authors study the degradation of MOSFET current-voltage (V-I) characteristics as a function of polysilicon gate concentration (N_p ), oxide thickness (t_ox) and substrate impurity concentration (N_D) using measured and modeled results. Experimentally it is found that for MOSFETs with thin gate oxide (t_ox≈70 Å) and high substrate concentration (N_D ≈1.6×10¹⁷ cm^-3) the reduction in the drain current I_DS can be as large as 10% to 20% for devices with insufficiently doped polysilicon gate (5×10¹⁸ ⩽N_p⩽1.6×10¹⁹ cm^-3). Theoretically it is shown that the drain current degradation becomes more pronounced as N_p decreases, t_ox decreases, or N_D, increases. A modified Pao-Sah model that takes into account the polysilicon depletion effect and an accurate gate-field-dependent mobility model are used to compute I-V characteristics for various values of N_p, t_ox, and N_D. Good agreement between experimental and modeled results is observed over a wide range of devices     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices