一种改进的神经网络自适应控制方法

本文提出了一种改进的神经网络的控制方法，该方法引入一个神经网络辨识器同时作了为神经网络控制器的输出层，从而可以直接通过系统的期望输出和实际输出之差来神经网络控制器的权值，更好地适应对象的非线性和变化。     

基于BP算法的多层前馈网络在质差建模中的应用

BP神经网络算法可以以任意精度逼近任何非线性函数,且具有并行分布存储、高度鲁棒性与容错能力,适合解决受多重因素交叉影响的复杂的非线性问题。主要提出了一种基于BP神经网络的预测方法,并详细阐述神经算法的基本原理、建模方法以及其在质差预测中的应用。     

基于自适应动态规划的一类非线性系统的容错控制器设计

针对存在执行器故障的一类仿射非线性系统,基于自适应动态规划方法,提出了一种新型的容错控制器。利用故障观测器估计执行器故障,并利用故障信息构建一个改进型的性能指标函数,将容错控制问题转化为最优控制问题。同时使用策略迭代(PI)算法,通过构造评价神经网络来求解HJB方程,获得近似最优容错控制律,并且基于李雅普诺夫函数,证明该容错控制器可以确保闭环系统渐近稳定。最后,通过仿真验证了该方法的有效性。     

军用通信网络可靠性设计技术

针对无法简单套用经典方法来研究复杂军用通信网可靠性设计这一难题,对通信网可靠性研究进行了分析,提出了详细的可靠性测度指标。基于军用通信网可靠性设计需求,建立了系统可靠性测度和数学模型,给出了一种快速的解析评估算法和适用于大型网络的模拟方法。仿真结果表明,该设计能够快速、有效地计算评估可靠性指标,为军用通信网络可靠性设计提供可行、有效的工程方法。     

一类非线性不确定时滞系统鲁棒容错控制

研究一类不确定非线性时滞系统的鲁棒容错控制问题.针对不确定非线性时滞系统,基于执行器连续型增益故障模式,利用Lyapunov-Krasovskii泛函方法和线性矩阵不等式方法,推导了当一类非线性不确定系统满足一定范数有界条件时,闭环系统时滞无关鲁棒容错控制器存在的充分条件,并给出了状态反馈鲁棒容错控制器的设计方法.将所设计的状态反馈控制方法应用于某一非线性不确定时滞系统,仿真结果表明设计的控制器不仅使得该故障系统对于执行器故障具有完整性,并且能达到给定的H∞性能指标,从而验证了所提出方法的可行性和有效性.     

一种改进的用于可靠性分析的神经网络的实现

针对容错系统的可靠性问题,建立基于马尔科夫模型的三层前馈神经网络。提出一种改进的神经网络训练算法,用于包含永久过错．瞬态过错和周期过错影响的一个三模冗余（TMR,Triple Modular Redundancy）系统的可靠性分析。一个全连接的三层神经网络表示一个容错系统的离散时间n状态马尔科夫模型的可靠性。将系统的期望可靠性反馈入网络,当神经网络收敛时,从神经网络的权值中得出设计参数。仿真结果显示,与四层神经网络相比．三层神经网络收敛得更快．收敛可靠十牛更椿沂期望可靠性。     

普遍故障下神经网络隐层冗余容错的分析与应用

隐层神经元冗余是提高神经网络容错性的一个有效的方法,在神经网络分类器的容错设计中,这一方法得到了良好的效果,对单故障可以做到完全容错.但是这一应用仅仅只能应用于输出层为硬限幅函数的前向网络,并且只证明了对网络中单故障有效.在实际应用中,网络中的各个节点和权值的故障往往是普遍存在的,因此本文提出了一种隐层冗余结构,对普遍故障存在下隐层神经元冗余容错方法做以评估,得出的结论是应用这种隐层神经元冗余结构可以减小网络的全局故障率;并提出了针对一般前向神经网络的实用的隐层神经元容错方法,这种方法可以有效地提高网络在普遍故障下的容错能力.     

基于滑模反步法的HSV被动容错控制设计

针对高超声速飞行器(HSV)无动力再入过程中舵面发生损伤故障的情况,设计了一种基于滑模反步法的姿态被动容错控制器。以公开的Winged-Cone飞行器非线性动态模型及其气动力与力矩为基础,对非线性模型进行时标分离处理,将姿态控制系统分解为姿态角速率与姿态角的快慢双回路系统。并以反步法为基础,结合滑模控制与动态面技术设计了被动容错控制器。通过Lyapunov稳定性分析以及数值仿真可知,所设计的被动容错控制器可以在没有任何损伤故障信息的情况下,保障姿态控制系统的稳定性与鲁棒性。     

实现标量混沌信号同步控制的神经网络方法

本文给出了一种利用线性输出神经网络实现标量混沌信号同步控制的方法。该方法利用线性输出神经网络构造被控混沌系统的模型，并基于Lyapunov理论与非线性系统控制方法，设计出神经网络权值变化规律与非线性反馈控制器，使神经网络模型的标量输出能大范围同步于给定的标量混沌信号。理论分析与计算机模拟结果都证实了这种方法的有效性。     

基于模型匹配的光电侦察无人机飞行控制器设计方法

无人机在光电侦察领域的应用越来越广泛,设计可靠的飞行控制器是完成侦察任务的必要手段。提出了一种基于模型匹配和遗传算法寻优的以非线性模型为被控对象的飞行控制器设计方法。通过该方法可以实现无人机飞行控制器与飞行仿真模型的一体化快速设计与仿真,与经典的飞行控制器设计方法相比,该方法能够比较快速、便捷地获得所需控制器。建立了包含气动、发动机和环境模型的某型无人机六自由度非线性全量数学模型,然后基于此模型,应用上述方法设计了无人机的飞行控制器,基于有限状态机理论建立了飞行管理模型,设计无人机飞行剖面并实现控制器切换,最后进行了六自由度非线性仿真,验证了所设计控制器的有效性。     

Probabilistic Design of Fault Tolerant Control via Parameterization

This paper studies the design of fault tolerant control systems (FTCSs) by considering random faults and two categories of design objectives. The FTCSs are modeled in a stochastic framework, resulting from the random fault process. The design objectives include a stability requirement and a probabilistic performance index. Such an index is chosen as a reliability-related criterion, which can be evaluated from a numerical procedure only but lacks analytical expressions. A parameterization procedure together with a randomization-based optimization method is developed to find a statistically optimal controller that can stabilize the system and achieve the highest reliability.     

Maintainability Considerations in a Fault Tolerant/Faultproof Systems Design

The maintainability, reliability, and availability of a computer system are closely bonded to insure continuing service of a system. The ability of a system to tolerate failures or faults while operating is a principal requirement of a fault tolerant system. A fault tolerant system's design must incorporate considerations for maintenance and reliability in order to provide its ultimate requirement-available operation. These factors are considered in the design philosophy presented in this paper, identified as FAULTPROOF. FAULTPROOF design incorporates redundancy, reliability, maintainability, and adaptability to augment normally accepted fault tolerant design. The design approach described utilizes a hierarchical interconnection mechanism, Intelligent Networked Partitioning, to isolate faulted components.     

用于低开销容错设计的存储部件可靠性评估研究

低开销容错技术是当前软错误研究领域的热点。为了对微处理器进行低开销容错保护,首先就需要对微处理器可靠性(即体系结构弱点因子AVF (Architectural Vulnerability Factor))进行准确评估。然而,现有的AVF评估工具的精确性和适用范围都受到不同程度的限制。该文以微处理器上的核心部件(即存储部件)作为研究对象,对AVF评估方法进行改进,提出了一种访存操作分析和指令分析相结合的AVF评估策略HAES (Hybrid AVF Evaluation Strategy)。该文将HAES融入到通用的模拟器中,实现了更精确和更通用的AVF评估框架。实验结果表明相比其它AVF评估工具,利用该文提出的评估框架得到的AVF平均降低22.6%。基于该评估框架计算得到的AVF更加精确地反映了不同应用程序运行时存储部件的可靠性,对设计人员对微处理器进行低开销的容错设计具有重要指导意义。     

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.     

Component Reliability Importance assessment on complex systems using Credible Improvement Potential

Nowadays system reliability performance represents a key issue and being reliable becomes a fundamental requirement of products in many manufacturing fields. The paper is focused on the reliability improvement of fault tolerant complex systems using component Reliability Importance (RI) procedures in order to assess the impact of each component on the overall system reliability. This study is focused on RI assessment during design stage with the aim of optimizing engineers' efforts and focusing on components with the greatest effect on the whole system. The first part of the paper focuses on a particular Reliability Importance measure, the Credible Improvement Potential (CIP), which is the most suitable RI metric for our purpose. The Reliability Importance assessment on a dedicated case study based on fault tolerant complex system is then proposed and results are discussed in detail.     

一种容错的空间计算机体系结构

当今空间计算机必须具有强实时下的高速处理能力和自主工作方式下的高可靠性，而对长寿命卫星而言，其可靠性要求使得任何一种模式的单机结构都难以胜任，于是各种各样的冗余方案溶进了星载计算机设计中，而有目的地识别和选择一种结构使其在有限资源的条件下最大限度地实现容错，同时又能达到所要求的性能，这正是本文所追求的目标，这里阐明的是一种模块化的容错结构，它使用简易的冗余内总线．将不同功能的冗余模块紧密地耦合在一起，从而使系统级的性能可以很方便的进行扩展，功能上可以灵活地实现集中或分布，从而达到了既适应空间计算和控制要求，又满足容错的性能要求的目标。     

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Due to shrinking feature size and higher transistor count in a single chip in modern fabrication technologies, power consumption and soft error reliability have become two critical challenges which chip designers are facing in new silicon integrated circuits. Recent studies have shown that these issues have compromising effects on each other. Besides, power consumption and reliability significantly vary across workloads and among pieces of a single application which can be exploited to design adaptive runtime fault tolerant and low power systems. These attractions have been exploited in prior studies to design online reconfigurable fault tolerant systems with power management schemes. However, those attempts are driven by complicated simulations and hardly deliver a sense of direction to the designers. To achieve maximum efficiency in terms of power, performance, and reliability in dynamic scaling of voltage and frequency, it is critical to have a simple and accurate reliability model which estimates the value of fault rate considering supply voltage and operating frequency of a circuit. In this paper, we propose an accurate formula for analytic modeling of the soft error rate of a system which can be used to precisely track the reliability of the system under dynamic voltage and frequency adjustments. The experimental results of this paper prove that our proposed model offers precise estimates of reliability in accordance with the results of accurate soft error rate (SER) estimation algorithm for ISCAS85’s benchmark circuits.     

Design and implementation of a fault tolerant controller for EMS systems

Conventional EMS (electromagnetic suspension) systems are susceptible to instability problems, and could even break down upon failures of the air-gap sensor or the accelerometer. Therefore, in order to improve EMS performance, a fault tolerant controller and a fault detection and isolation (FDI) algorithm are presented in this work. The fault tolerant controller is an extended version of the linear fault tolerant controller designed for known actuator or sensor failures, and it adopts the LMI-based H_∞ control for a class of nonlinear systems. The fault detection algorithm employs fuzzy inference. The merits of the proposed control scheme have been verified by the experiments with a single-axis two-magnet suspension system subjected to failures of the actuator or the sensors.     

Fault‐tolerant spanners for ad hoc networks

Spanners for ad hoc networks provide several benefits such as low communication cost and resource consumption. These spanners need to be fault tolerant in resource‐constrained ad hoc networks. In this paper, we have proposed three spanners, called fault‐tolerant local Delaunay triangulation (FTLDel), fault‐tolerant relative neighborhood graph (FTRNG), and fault‐tolerant Gabriel graph (FTGG). The fault‐tolerant spanners provide reliability to the network by avoiding heavy packet loss and retaining useful geometric properties. The performance of fault‐tolerant spanners FTLDel, FTRNG, and FTGG are evaluated using the network simulator ns2.28. Copyright © 2011 John Wiley & Sons, Ltd.     

Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis

Recent literatures have proved that current technologies pose grave reliability concern for digital devices due to possibility of multiple (k_m)-unit transient fault (MTF) and multi (k_c)-cycle transient fault (MCT) emanating from particle strike with moderate linear energy transfer (LET). This has arisen due to massive scaling in device dimensions and surge in device frequency happening so far. In the literature solutions for fault tolerant design, that can address MTF and MCT simultaneously during high level synthesis (HLS) for both loop based and non-loop based applications, does not exist. This paper presents the following novel contributions: (a) novel fault tolerant HLS methodology for simultaneously providing multi-cycle (control step) and multi-unit transient fault tolerance for loop based control data flow graphs (b) novel HLS methodology for low cost design solution through exploration of fault tolerant hardware configuration and loop unrolling factor. Results of the proposed approach on standard benchmarks yielded fault tolerant solutions with significantly reduced design cost (average ~ 27%) and power consumption (average ~ 61%) when compared to a recent similar approach.