功率VDMOS器件的SEB致SEGR效应研究

功率VDMOS器件是航天器电源系统配套的核心元器件之一,在重粒子辐射下会发生单粒子烧毁(SEB)和单粒子栅穿(SEGR)效应,严重影响航天器的在轨安全运行。本文在深入分析其单粒子损伤机制及微观过程的基础上,发现了功率VDMOS器件在重粒子辐射下存在SEBIGR效应,并在TCAD软件和¹⁸¹Ta粒子辐射试验中进行了验证。引起该效应的物理机制是,重粒子触发寄生三极管,产生瞬时大电流,使得硅晶格温度升高,高温引起栅介质层本征击穿电压降低,继而触发SEGR效应。SEBIGR效应的发现为深入分析功率MOSFET器件的单粒子辐射效应奠定了理论基础。     

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation.The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range(-55 to 150℃).An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism.The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature.The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.     

功率MOS和IGBT器件在无嵌位电感开关条件下的动态雪崩特性研究

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.     

SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application.Single event gate rupture (SEGR) and single event burnout (SEB),which will degrade the running safety and reliability of spacecraft,are the two typical failure modes in power MOSFETs.In this paper,based on recombination mechanism of interface between oxide and silicon,a novel hardened power MOSFETs structure for SEGR and SEB is proposed.The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers.Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50％ when the linear-energy-transfer value of heavy ion is a constant of 98 MeV.cm2/mg in the whole incident track,and the other parameters are almost maintained at the same value.Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.     

A¨nalysis of floating body effects in thin film conventionaland single pocket SOI MOSFETs using the GIDL current technique

Using a novel gate-induced-drain-leakage (GIDL) current technique and two-dimensional (2-D) simulations, single pocket (SP) SOI MOSFETs have been shown to exhibit reduced floating body effects compared to the homogeneously-doped channel (conventional) SOI MOSFETs. The GIDL current technique has been used to characterize the parasitic bipolar transistor gain for both conventional and SP-SOI MOSFETs. From 2-D device simulations, the lower floating body effects in SP-SOI MOSFETs are analyzed and compared with the conventional MOSFETs     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Photon emission as a characterization tool for bipolar parasitics in FinFET technology

Parasitic bipolar effects are a well-known failure mechanism in integrated circuits. They trigger latching phenomena and are of particular interest for higher current applications and under leaky conditions. Photon emission microscopy (PEM) has proven to be a suitable tool to detect the occurrence of parasitic bipolar elements in MOSFETs, such as the parasitic bipolar junction transistor (BJT). Spectral PEM even allows for a more detailed characterization of the respective parasitic bipolar operation modes. In this work, we show that spectral PEM can also be used to characterize bipolar parasitics in modern p-type and n-type FinFETs. Additionally, this characterization method allows us to determine whether germanium enriched silicon was used to optimize device performance. We conclude by demonstrating that the FinFET devices under test show a very good suppression of parasitic bipolar effects.     

Exploration of heavy ion irradiation effects on gate oxide reliability in power MOSFETs

Heavy ion irradiation effects on gate oxide reliability in power MOSFETs were explored. Devices were exposed to heavy ion fluences and LETs simulating exposure in spacecraft at bias levels not expected to cause catastrophic failure. Time dependent dielectric breakdown measurements and charge separation techniques resulted in no detectable changes. The gate voltage at which oxide breakdown occurs and the gate I–V curves suggest subtle changes in device characteristics that can be detected at high gate biases. However, there is no indication that heavy ion exposure results in a significant reduction in gate oxide reliability.     

The SINFET: a new high conductance, high switching speed MOS-gated transistor

A new MOS power semiconductor device with a very low on-resistance and a switching speed comparable to conventional n-channel power MOSFETs is described. The fabrication process is similar to that of an n-channel lateral DMOS transistor but with the conventional high-low `ohmic? drain contact replaced by a Schottky contact. In operation, the Schottky contact injects minority carriers to conductivity-modulate the n- drift region, thereby reducing the on-resistance by a factor of about ten compared with those of conventional n-channel power MOSFETs of comparable size and voltage capability. Furthermore, since only a small number of minority carriers are injected, the device speed is comparable to conventional n-channel power MOSFETs.     

Evolution of MOS-bipolar power semiconductor technology

A review of the innovations that have led to the evolution of a power transistor technology based on MOS gate control is provided. This technology offers the advantage of very high input impedance, which allows the control of the devices using low-cost integrated circuits. The physics of operation of the two types of devices in this category, power MOSFETs and power MOS-bipolar devices, are described. Trends in process technology and device ratings are analyzed. Based on the superior performance of these devices, it is projected that they will completely displace the power bipolar transistor in the future     

Low-voltage transient bipolar effect induced by dynamicfloating-body charging in scaled PD/SOI MOSFETs

An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 μm SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems     

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation.The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source).The simulation result shows that the proposed structure can enhance the SEB survivability significantly.The critical value of linear energy transfer (LET),which indicates the maximum deposited energy on the device without SEB behavior,increases from 0.06 to 0.7 pC/μm.The SEB threshold voltage increases to 120 V,which is 80％ of the rated breakdown voltage.Meanwhile,the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure.Therefore,this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

国产中高压抗辐照功率MOSFET单粒子效应

功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明：对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。     

Monolithic integration of a high-performance clustered insulated gate bipolar transistor with low-voltage components to form a 3 kV intelligent power chip

For the first time, we evaluate the feasibility of monolithic integration of low-voltage components, such as n and p channel MOSFETs, into a 3 kV novel planar power semiconductor device, called the clustered insulated gate bipolar transistor, to realise an intelligent power chip. The power device employs MOS control with a thyristor to lower the on-state conduction losses and a unique self-clamping feature that provides current saturation at high gate voltages and enables the incorporation of low-voltage devices without any additional processing. This combination paves the way for realising an intelligent power chip with enhanced performance with respect to on-chip temperature, over-current and over-voltage protection circuitry.     

Thermal modeling of single event burnout failure in semiconductor power devices

Experimental investigations of single event burnout (SEB) of power devices due to heavy ion impacts have identified the conditions required to produce device failure. A key feature observed in the data is an anomalistic secondary rise in current occurring shortly after the ion strike. To verify these findings including the thermally induced secondary plateau, simulations have been performed on the model single event burnout. The new models include additional thermally dependent electrical components to capture thermally induced physical effects. Through the inclusion of analytic temperature models coupled with the electrical model, the electrical response is predicted with reasonable accuracy. The simulations provide order-of-magnitude estimates as well as prediction of phenomenological features such as the secondary rise in current. This work represents a first attempt to characterize thermal failure of power devices due to heavy ion impacts by including temperature dependent components that until now have not been modeled. The thermal model in the present work produces qualitative agreement with experiments on SEB that have been previously unexplained.     

Dynamics of power MOSFET switching under unclamped inductiveloading conditions

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p⁺ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions     

A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.     

Hot-carrier effects and lifetime prediction in off-state operationof deep submicron SOI N-MOSFETs

Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original V_t variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low V_d range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high V_d, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability     

A three-step method for the de-embedding of high-frequencyS-parameter measurements

The authors propose a general method of deembedding S-parameter measurements of the device-under-test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement. The DUT is the analog silicon bipolar junction transistor including the pad and interconnects. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters on the on-wafer open circuit which are taken from measurements of the short and through circuits. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (⩾10 GHz). A knowledge of the magnitude and type of parasitic deembedding circuit elements can aid the device engineer in the analysis of the error associated with deembedding