Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

Sub-mA single ended CMOS low noise amplifier with 2.41 dB noise figure

This paper presents a single ended low noise amplifier (LNA) using 0.18 μm CMOS process packed and tested on a printed circuit board. The LNA is powered at 1.0 V supply and drains 0.95 mA only. The LNA provides a forward gain of 11.91 dB with a noise figure of only 2.41 dB operating in the 0.9 GHz band. The measured value of IIP3 is 0.7 dBm and of P1dB is −12 dBm. Zhang Liang is currently with Cyrips, Singapore. Ram Singh Rana was born in Delhi (India). Having primary education in Bijepur, Dwarahat(India), he received the B.Tech. (hons.) degree in Computer Engineering from G.B. Pant University, Pantnagar, India in 1988 and the Ph.D degree from the Indian Institute of Techonology (IIT), Delhi, India in 1996. He worked for his Ph.D in the Centre for Applied Research in Electronics, IIT Delhi in close interaction with the Semiconductor Complex Limited, Mohali, India. He was with ESPL, Mohali(India) in 1988 for a very short period and then served IIT Delhi as Senior Research Associate (88-90) and Senior Scientific Officer (90-95) where his main contributions were on CMOS analog IC design in subthreshold operation. He was a Lecturer in the Kumaon Engg. College, Dwarahat (India) before serving the IIT Roorkee (Formerly Univ. of Roorkee) in 1998 as assistant Professor. In 1999, he was a Manager (Engineering), Semiconductor Product Sector of the Motorola, Noida, India. Since joining the Institute of Microelectronics, Singapore in 2000, he worked mostly on RFICs, Fractional-N PLLs, ADCs. During 2001-2004, he worked there as IC Design Research and Training Program Manager. Currently, he is serving the institute as Senior Research Engineer in CMOS IC design (below 1V) for biomedical and bio-sensors. His current interests include design and consultancy for CMOS ICs/systems for the biomedical and high speed communication applications. Dr. Rana received Young Teacher Career Award from the All India Council for Technical Education in 1997. He was an Adjunct Asstt. Professor with the National University of Singapore (NUS), Singapore in 2004. He is sole inventor of two US granted patents and has filed several other patents. He has authored/co-authored about 40 publications. He has been reviewer for several IEEE journals and conference papers. Dr Rana is a senior member of IEEE and a member of Graduate Program in BioEngineering, NUS Singapore. He has chaired /co-chaired sessions in many international conferences. Zhang Liang was born in China in June 1978. He received the Bachelor degree and the Master degree in Electrical Engineering from the Xi’an JiaoTong University, Xi’an, China, in 2000 and 2003 respectively. Since 2003, he has been a postgraduate student in the Electrical and Computer Engineering department, National University of Singapore(NUS), Singapore and has successfully completed M.Engg degree program of the NUS. He is currently working on RFICs as a design engineer in Cyrips, Singapore. His design and research interests include integrated circuit design for communications. He has authored/co-authored several publications of international standard. Hari K Garg obtained his BTech degree in EE from IITDelhi in 1981. Subsequently, he obtained his MEng & PhD degrees from Concordia University in 1983 & 1985, and MBA from Syracuse University in 1985. He was a faculty member at Syracuse University from 1985 till 1995. He has been with the National University of Singapore since 1995 till present with the exception of 1998-1999 when he was with Philips. Hari’s research interests are in the area of digital signal/image processing, wireless communications, coding theory and digital watermarking. He has published extensively on these and related topics. He is also founder of several companies in the space of mobile telephony. In his spare time, Hari enjoys singing and a good game of Squash.     

P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter

In flip-chip design, voltage drop reduction in the power ground network has become a challenging problem particularly in the modern Multiple Supply Voltage(MSV) designs. An effective P/G network design and floorplanning- based solutions helps to produce a quality power plan in the layout. Hence, this paper proposes an iterative MSV floorplanning methodology that performs modifications in the existing floorplan representation that satisfies the voltage island constraint and produce an IR drop-aware quality layout. Furthermore, the proposed methodology is integrated with commercial tool design flow to analyze the reduction of IR drop in the layout. Two simulation-based experiments are performed in this paper to showcase the significance of this work. Firstly, it presents the simulation results that benchmark the proposed idealogy in non-flip chip designs. Secondly, the presented framework is integrated in flip-chip layouts of FIR design operating with two voltage islands for low power consumption. To understand the ability of the proposed floorplanning approach, the simulation were performed for two different sized P/G mesh structure for various mesh width. Experimental results from both simulations demonstrate that the proposed MSV floorplanning technique is effective in reducing IR drop while optimizing the design for low power dissipation.

     

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-μm operational transconductance amplifiers having equal 50-μA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz^1/2, and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes. David M. Binkley (S’81, M’82, SM’93) joined the University of North Carolina at Charlotte in 2000 as an associate professor in the electrical and computer engineering department. Dr. Binkley and his students are researching analog design and testing methodologies including micropower, low-noise analog CMOS design for neural implants and radiation hardened, deep space applications. Dr. Binkley was a cofounder and vice president of integrated circuit development at Concorde Microsystems and senior scientist at CTI PET Systems where he designed both discrete and integrated CMOS electronics for positron emission tomography (PET) medical imaging systems. Concorde and CTI are currently part of Siemens Medical Solutions. Dr. Binkley received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville. He is the author of over 60 papers in analog circuit design and instrumentation and holds five U.S. patents. Dr. Binkley is currently writing the book, Analog CMOS Design, Tradeoffs and Optimization, for John Wiley and Sons with planned publication in 2006. Benjamin J. Blalock (S’, M’) received his B.S. degree in electrical engineering from the University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He joined the Department of Electrical and Computer Engineering at Mississippi State University in 1996 and the University of Tennessee in 2001. His current research focus includes mixed-signal/mixed-voltage circuit design for systems-on-a-chip in SOI technology, analog IC design for extreme environments, multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, and bio-microelectronics. He has over 25 publications in the field of analog IC design and has contributed to The Circuits and Filters Handbook. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems, Inc. James M. Rochelle (M’84) received the B.S., M.S., and Ph.D. degrees in Electrical engineering from the University of Tennessee, Knoxville. From 1965 to 1982 he was with the Instrumentation and Controls Division of the Oak Ridge National Laboratory. From 1982 to 2001, he was Associate Professor of Electrical and Computer Engineering at the University of Tennessee, Knoxville teaching and conducting research in integrated circuit device modeling and mixed-signal integrated circuit design. In 2001 he retired from academia and is presently an emeritus associate professor and vice president of ASIC development at Concorde Microsystems, Inc., now part of Siemens Medical Solutions located in Knoxville, Tennessee. His current research interests are mixed-signal ASIC's for medical imaging readout electronics and micropower battery-powered devices.     

Cycle-Accurate Energy Measurement and Characterization of FPGAs

Field Programmable Gate Arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip (SoC) designs. Nevertheless, FPGA vendors cannot accurately specify the power consumption of their products on device data sheets because the power consumption of FPGAs is strongly dependent on the target circuit, including resource utilization, logic partitioning, mapping, placement and routing. Although major CAD tools have started to report average power consumption under given transition activities, power-efficient FPGA design demands more detailed information about power consumption. In this paper, we introduce an in-house cycle-accurate FPGA energy measurement tool and energy characterization schemes spanning low-level to high-level design. This tool offers all the capabilities necessary to investigate the energy consumption of FPGAs for operation-based energy characterization, which is applicable to high-level and system-wide energy estimation. It also includes features for low-level energy characterization. We compare our tool with Xilinx XPower and demonstrate the state-machine-based energy characterization of an SDRAM controller.The RIACT at Seoul National University provide research facilities for this study. This work was partly supported by the Brain Korea 21 Project.Hyung Gyu Lee received the B.S. degree in Dept. of Computer Engineering from DongGuk University, in 1999, M.S. degree in School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2001, and is currently working toward the Ph.D. degree at Seoul National University. His research interests include device-level energy measurement and characterization, system-level low power design and low-power FPGA design.KyungSoo Lee is a M.S. student at the School of Computer Science and Engineering, Seoul National University. He received the B.S. degree in the School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2004. He is currently working on low-power systems and embedded systems for his M.S. degree.Yongseok Choi received the B.S. and M.S. degree in the School of Computer Science and Engineering from Seoul National University, Seoul, Korea, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree in the School of Computer Science and Engineering at Seoul National University. His research interests include embedded systems and low power systems.Naehyuck Chang received his B.S., M.S. and Ph.D. degrees all from Dept. of Control and Instrumentation Engineering, Seoul National University, Seoul, Korea, in 1989, 1992 and 1996, respectively. Since 1997, he has been with School of Computer Science and Engineering, Seoul National University and currently is an Associate Professor. His research interest includes system-level low-power design and embedded systems design.     

Performance Simulation of a Microwave Micro-Electromechanical System Shunt Switch Using Chatoyant

In this paper we demonstrate the capabilities of our mixed-signal, multi-domain system level simulation tool, Chatoyant, to model and simulate an RF MEMS shunt switch. We verify our mechanical simulations and analysis by comparison to results from commercial simulation packages, ANSYS and CoventorWare. We show that our modeling accuracy and simulation speed are comparable to these commercial tools for specific analysis. We conclude by showing the unique capabilities of a system tool based on a modular hierarchal approach that allows one to model not only the individual components of the system but also the subtle interactions resulting in specific system behaviors.Michael Bails received his B.A. in Economics from the University of Vermont in 1995 and a B.S. in Electrical Engineering from the University of Pittsburgh in 2002 (cum laude). He worked as an undergraduate researcher in optical MEMS for Benchmark Photonics, a Pittsburgh-based start-up company from 2001 to 2002. Mr. Bails is currently pursuing his M.S. in the Department of Electrical and Computer Engineering at the University of Pittsburgh, where he is a recipient of the Rath Fellowship. His interests are in MEMS modeling with an emphasis on statistical process variations. Mr. Bails is a student member of IEEE.José A. Martínez is an Electrical Engineering Ph.D. student at the University of Pittsburgh. He received his MS from the University of Pittsburgh (2000) in Electrical Engineering. He received the BS (magna cum laude) in Electrical Engineering from the Universidad de Oriente (UDO), Venezuela, in 1993. Mr. Martínez was granted the José Feliz Rivas’ medal for high academic achievement by the Venezuelan government (1993), and scholarships by the Venezuelan Fundayacucho Society (1993) and CONICIT-UDO (1994) institution. Since 1997 he has been working in the Optoelectronic computing group at the University of Pittsburgh. His research interests include behavioral simulation, reduction order techniques, modeling of MEMs and OMEMs, CAD, VLSI and computer architecture. Mr. Martínez is a member of IEEE/LEOS, and OSA.Steven P. Levitan is the John A. Jurenko Professor of Computer Engineering in the Department of Electrical and Computer Engineering. He received the B.S. degree from Case Western Reserve University in 1972. From 1972 to 1977 he worked for Xylogic Systems designing hardware for computerized text processing systems. He received his M.S. and Ph.D. in Computer Science from the University of Massachusetts, Amherst. During that time he also worked for Digital Equipment Corporation, and Viewlogic Systems, as a consultant in HDL simulation and synthesis. He was an Assistant Professor from 1984 to 1986 in the Electrical and Computer Engineering Department at the University of Massachusetts. In 1987, Dr. Levitan joined the Electrical Engineering faculty at the University of Pittsburgh where he holds a joint appointment in the Department of Computer Science. He is Past Chair of the ACM Special Interest Group on Design Automation (SIGDA). He was awarded the ACM/SIGDA Distinguished Service Award for over a decade of service to ACM/SIGDA and the EDA Industry in 2002. He is on the technical advisory board for The Technology Collaborative. He is a senior member of the IEEE/Computer Society and a member of the Optical Society of America, the Association for Computing Machinery, and the International Society for Optical Engineering. He is a member of the ACM/IEEE Design Automation Conference Executive Committee.Jason Boles received the B.S. degree in computer engineering from the University of Pittsburgh, Pittsburgh, PA, in 2001, where he is currently pursuing the M.S. degree in electrical engineering. His research interests include hardware acceleration techniques for simulation, system level modeling, computer-aided design (CAD), as well as systems-on-chip design and verification. Mr. Boles is a student member of IEEE.Ilya V. Avdeev is currently with ANSYS, Inc (Canonsburg, PA). He received his B.S. and M.S. degrees both in mechanical engineering from St. Petersburg State Polytechnical University (Russia) in 1997 and 1999 respectively. He received his Ph.D. in mechanical engineering from the University of Pittsburgh in 2003. His dissertation was on modeling strongly-coupled MEMS. He has been an inaugural John Swanson Doctoral Fellow and was awarded numerous scholarships and personal grants during his undergraduate and graduate studies. His research interests include mathematical modeling of coupled-field effects, new finite element techniques and methods, design and simulation of MEMS/NEMS, and acoustics. He is a member of ASME and IEEE.Michael R. Lovell is the Associate Dean for Research and an Associate Professor of Industrial and Mechanical Engineering in the School of Engineering at the University of Pittsburgh. Dr. Lovell received his PhD in Mechanical Engineering in 1994 from the University of Pittsburgh. He joined the Mechanical Engineering Department at Pittsburgh in January of 2000 after three years of service as an Assistant Professor at the University of Kentucky and four years of service as a senior development engineer at ANSYS Inc. Professor Lovell is a W. K. Whiteford Endowed Faculty Fellow, has served as the Executive Director of the Swanson Center for Product Innovation since May of 2000, and has been the Director of the Swanson Institute for Technical Excellence since September of 2002. Among his accomplishments, Professor Lovell is a recipient of the NSF CAREER award (1997), the SME Outstanding Young Manufacturing Engineer Award (1999), and won the FAG Outstanding International Publication on Bearings (1998). Dr. Lovell’s primary research interests are in the areas of tribology, advanced computation, and micro and nano systems.Donald M. Chiarulli, Professor of Computer Science. Dr. Chiarulli received his BS degree (Physics, 1976) from Louisiana State University, MSc (Computer Science, 1979) from Virginia Polytechnic Institute, and PhD (Computer Science, 1986) from Louisiana State University. He was an Instructor/Research Associate at LSU from 1979 to 1986, and has been at the University of Pittsburgh since 1986. Dr. Chiarulli’s research interests are in photonic and optoelectronic computing systems architecture. Dr Chiarulli’s research has been recognized with Best Paper Awards at the International Conference on Neural Networks (ICNN-98) and the Design Automation Conference (DAC-00). He is also the co-inventor on three patents relating to computing systems and optoelectronics. He has served on the technical program committees of numerous conferences for both research and education issues. Dr. Chiarulli serves on the editorial board of the Journal of Parallel and Distributed Systems and is a member of the IEEE. SPIE, and OSA.     

On the Performance Analysis of a Class of Neuron Circuits

A new performance metric, Peak-Error Ratio (PER) has been presented to benchmark the performance of a class of neuron circuits to realize neuron activation function (NAF) and its derivative (DNAF). Neuron circuits, biased in subthreshold region, based on the asymmetric cross-coupled differential pair configuration and conventional configuration of applying small external offset voltage at the input have been compared on the basis of PER. It is shown that the technique of using transistor asymmetry in a cross-coupled differential pair performs on-par with that of applying external offset voltage. The neuron circuits have been experimentally prototyped and characterized as a proof of concept on the 1.5 μm AMI technology. Amit K. Gupta received his B.Tech. in Electrical Engineering from the Indian Institute of Technology Kanpur, India, in 2000 and the M.Sc. (Engg.) in Microelectronics from the Indian Institute of Science, Bangalore, India in 2004. He joined the Semiconductor Products Sector, Motorola (currently Freescale Semiconductor), India, in 2000, where he is currently working as a Design Engineer. His research interest includes low power analog circuit design and neuromorphic engineering. Navakanta Bhat received his B.E. in Electronics and Communication from University of Mysore in 1989, M.Tech. in Microelectronics from I.I.T. Bombay in 1992 and Ph.D. in Electrical Engineering from Stanford University, Stanford, CA in 1996. Then he worked at Motorola's Networking and Computing Systems Group in Austin, TX until 1999. At Motorola he worked on logic technology development and he was responsible for developing high performance transistor design and dual gate oxide technology. He joined Indian Institute of Science, Bangalore in 1999 where he is currently Assistant Professor in the Electrical Communication Engineering department. His current research is focused on Analog and RF Microsystems using CMOS and MEMS technology. The work includes process development, device design and modeling, circuit design. He has several research publications in international journals and conferences and 2 US patents to his credit. He is the recipient of the Young Engineer Award (2003) from the Indian National Academy of Engineering. He is currently the chair of the IEEE Electron Devices and Solid-State Circuits society, Bangalore chapter which has been recognized as the Outstanding Chapter of the Year (2003) by the IEEE SSC society.     

Distributed topology control of wireless networks

We propose and analyaze a distributed control law that will maintain prescribed local properties of a wireless ad hoc network in the presence of node mobility, MAC layer power control and link fades. The control law uses a simple and intuitive power adaptation mechanism. We consider as an example the topology requirement of maintaining the out-degrees of each node at prescribed values and keeping the in-degree close to the out-degree. The topology objective is achieved by adapting the transmission power based only on local information. This power adaptation algorithm is analyzed using the o.d.e. approach to stochastic approximation. Simulation results verify the analysis and demonstrate its effectiveness. We also study the ability of the proposed objective to maintain connectivity. Although many heuristics are described in the literature to maintain local topological properties, the algorithm proposed in this paper is the first one that has proven convergence properties. Vivek S. Borkar got his B. Tech. (Elec. Engg.) from Indian Institute of Technology, Mumbai, in 1976, M. S. (Systems and Control) from Case Western Reserve Uni. in 1977 and Ph.D. (Elec. Engg. and Comp. Sci.) from Uni. of California, Berkeley. He was with Uni. of Twente (1980–81), TIFR Centre, Bangalore (1982–89), Indian Inst. of Science (1989–99), and has been with School of Technology and Computer Science, Tata Inst. of Fundamental Research, Mumbai, since April 1999. His research interests include stochastic optimization and applications. D. Manjunath received his B.E. from Mysore University, M.S. from Indian Institute of Technology, Madras and Ph.D. from Rensselaer Polytechnic Inst, Troy NY in 1986, 1989 and 1993 respectively. He has been a summer intern in the Corporate R & D Center of GE (1990), a visiting faculty in the Computer and Information Sciences Dept. of the University of Delaware (1992-93), a post doctoral fellow in the Computer Science Dept. of the University of Toronto (1993–84) and on the Electrical Engineering faculty of the Indian Inst. of Technology, Kanpur (1994–98).He has been with the Elec Enggg. Dept. of Indian Inst. of Technology, Bombay in Mumbai since July 1998 where he is now an Associate Professor. His research interests are in the areas of communication networks, performance analysis of systems, queueing systems and multimedia communications.     

VLSI计算机辅助设计框架──面向对象的DO模型及EOIDE框架的开发

本文叙述了一种新的集成电路计算机辅助设计框架的设计思想：提出了符合集成电路设计需要的新的四维数据模型，并设计了面向对象的工程数据库；提出了便于在框架中集成已开发完成的ＩＣ设计工具的松耦合的集成方式。讨论了用户管理、设计数据的版本管理以及在层次设计、多用户环境下的并发控制等在框架实施中的问题，提出了处理方案。基于上述思想，在ＨＰ／８００工作站ＵＮＩＸ操作系统下开发了集成电路设计框架ＥＯＩＤＥ（Ｅｎｔｉｔｙ－ＯｒｉｅｎｔｅｄＩＣＩｎｔｅｇｒａｔｅｄＤｅｖｅｌｏｐｍｅｎｔＥｎｖｉｒｏｎ－ｍｅｎｔ），并在框架上装入了单层门阵列设计工具（ＥＮＹＡ），设计了单层门阵列电路，结果良好。     

PAD: A New Interactive Knowledge-Based Analog Design Approach

This paper presents a new Procedural Analog Design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimize design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. Its interactive interface enables instantaneous visualization of design tradeoffs. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimized design is ready for simulation (verification and fine-tuning). The present version of PAD covers the design of basic analog structures (one transistor or groups of transistors) and the procedural design of transconductance amplifiers (OTAs) and different operational amplifier topologies. The basic analog structures calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way [1, 2]. Furthermore, PAD provides a layout generator for matched substructures such as current mirrors, cascode stages and differential pairs.Danica Stefanovic was born in 1976. She received the B.S. and M.S. degrees in electrical engineering from the University of Nis (Serbia and Montenegro) in 2000 and 2003 respectively. In 2001/2002 she was a scholarship holder of Swiss Confederation working with Electronic Laboratories, Swiss Federal Institute of Technology (EPFL), on a research project in the domain of analog circuits design techniques and their translation into specific CAD tool. She is currently working towards Ph.D. degree at the Swiss Federal Institute of Technology (EPFL). Her research interests include low power, low voltage analog design methodologies and optimisation techniques.Maher Kayal was born in 1959. He received the M.S. and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology (EPFL, Switzerland) in 1983 and 1989 respectively.In 1990, he had a Research Associate in the Swiss Federal Institute of Technology. From 1999 he became a professor in the Electronics Laboratories of this institute. He has published many scientific papers and contributed in three books dedicated to mixed-mode CMOS design. His current research interests include: mixed-mode circuit design, sensors, signal processing and CAD tools for analog design and layout automation. He received in 1990 the Swiss Ascom award for the best work in telecommunication fields and in 1997 the best ASIC award at the European Design and Test Conference ED&TC.Marc Pastre was born in 1977. He received the M.S. degree in computer science at EPFL (Swiss Federal Institute of Technology) in 2000. He is currently working towards his Ph.D. at the Electronics Laboratories LEG (EPFL). His research interests include mixed circuits, ADCs/DACs, sensor frontends and CAD tools.     

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications. Michael Schulte received a B.S. degree in Electrical Engineering from the University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless systems. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing. John Glossner is CTO & Executive Vice President at Sandbridge Technologies. Prior to co-founding Sandbridge, John managed the Advanced DSP Technology group, Broadband Transmission Systems group, and was Access Aggregation Business Development manager at IBM’s T.J. Watson Research Center. Prior to IBM, John managed the software effort in Lucent/Motorola’s Starcore DSP design center. John received a Ph.D. in Computer Architecture from TU Delft in the Netherlands for his work on a Multithreaded Java processor with DSP capability. He also received an M.S. degree in Engineering Management and an M.S.E.E. from NTU. John also holds a B.S.E.E. degree from Penn State. John has more than 60 publications and 12 issued patents. Dr. Sanjay Jinturkar is the Director of Software at Sandbridge and manages the systems software and communications software groups. Previously, he managed the software tools group at StarCore. He has a Ph.D in Computer Science from University of Virginia and holds 20 publications and 4 patents. Mayan Moudgill obtained a Ph.D. in Computer Science from Cornell University in 1994, after which he joined IBM at the Thomas J. Watson Research Center. He worked on a variety of computer architecture and compiler related projects, including the VLIW research compiler, Linux ports for the 40x series embedded processors and simulators for the Power 4. In 2001, he co-founded Sandbridge Technologies, a start-up that is developing digital signal processors targeted at 3G wireless phones. Suman Mamidi is a graduate student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He received his M.S. degree from the University of Wisconsin-Madison in December, 2003 and is currently working towards his PhD. His research interests include low-power processors, hardware accelerators, multithreaded processors, reconfigurable hardware, and embedded systems. Stamatis Vassiliadis was born in Manolates, Samos, Greece, in 1951. He is currently a Chair Professor in the Electrical Engineering, Mathematics, and Computer Science (EEMCS) department of Delft University of Technology (TU Delft), The Netherlands. He previously served in the Electrical and Computer Engineering faculties of Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. For a decade, he worked with IBM, where he was involved in a number of advanced research and development projects. He received numerous awards for his work, including 24 publication awards, 15 invention awards, and an outstanding innovation award for engineering/scientific hardware design. His 73 USA patents rank him as the top all time IBM inventor. Dr. Vassiliadis is an ACM fellow, an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences (KNAW).     

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little smart logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.Jeffrey Draper is a Research Assistant Professor in the Department of Electrical Engineering at the University of Southern California. He holds this appointment in conjunction with a Project Leader position at the Information Sciences Institute of the University of Southern California. Dr. Drapers research group has participated in many DARPA-sponsored large-scale VLSI development efforts. He is a member of the IEEE Computer Society and has conducted research in the areas of processing-in-memory architectures, thermal management, VLSI, interconnection networks, and modeling/performance evaluation. Dr. Draper received a BSEE from Texas A&M University and an MS and PhD from the University of Texas at Austin.J. Tim Barrett is a Senior Electrical Engineer at the Information Sciences Institute of the University of Southern California. Mr. Barrett has managed, designed and implemented the hardware, low-level software and integration of many computer systems. Applications of these systems include scalable supercomputers at USC Information Sciences Institute, the long distance telephone switch at AT&T Bell Labs, building energy management at Barber-Colman Company, and laser entertainment performance instruments at Aura Technologies and Laser Images Inc. He is a member of IEEE Solid State Circuits Society and received his MSCS from the University of Illinois Chicago and BSEE from the University of Iowa.Jeff Sondeen is a Research Associate at the Information Sciences Institute of the University of Southern California, where he supports and maintains CAD technology files, libraries, and tools for implementing VLSI designs. Previously he has worked at Silicon Compilers and Hewlett-Packard in CAD tool and test chip development. He received an MSEE from the University of Michigan.Sumit Mediratta is currently pursuing a PhD in Electrical Engineering at the University of Southern California. He received a Bachelor of Engineering degree in Electronics and Telecommunication from the Shri Govind Ram Sekseria Institute of Technology and Science, India. His research interests include interconnection networks, VLSI, processing-in-memory architectures, high-speed data communication and synchronization techniques and network interfaces for high-performance architectures.Chang Woo Kang received a BS in electrical engineering from Chung-ang University, Seoul, South Korea, in 1997 and an MS in electrical engineering from the University of Southern California, Los Angeles, in 1999. He is currently pursuing a PhD in electrical engineering at the University of Southern California. His research includes VLSI system design and algorithms for low-power logic synthesis and physical design.Ihn Kim is a PhD student in the Department of Electrical Engineering at the University of Southern California. He is also a Staff Engineer at QLogic. His research interests include user-level network interface, network processor architectures, and modeling/performance evaluation of system area networks. He is a member of the IEEE Computer Society. He received an MS at KAIST (Korea Advanced Institute of Science and Technology).Gokhan Daglikoca is an Application Engineer at Cadence Design Systems, Inc, where he specializes in High-Performance ASIC and Microprocessor Design Methodologies. He is a member of IEEE. Gokhan Daglikoca received a BS from Istanbul Technical University and an MS from the University of Southern California.     

一种用于暗域交替式相移掩模设计的自适应版图划分方法

提出了一种新的用于加速 1 30 nm以下工艺交替式相移掩模设计流程的版图划分方法 ,该方法能够自适应调整版图划分的粒度 .讨论了消除相位冲突的方法和版图压缩中相位兼容性保持的策略 .利用上述算法实现的 CAD原型系统经多个工业界例子的测试表明能够有效地适应随版图尺寸而快速增长的相位冲突复杂性 ,同时提供较好的 PSM设计质量 ,并能满足不同求解精度和加速比的要求     

A Video Streaming System for Mobile Phones: Practice and Experience

This paper presents a case of video streaming system for mobile phone which has actually been implemented and deployed for commercial services in CDMA2000 1X cellular phone networks. As the computing environment and the network connection of cellular phones are significantly different from the wired desktop environment, the traditional desktop streaming method is not applicable. Therefore, a new architecture is required to suit the successfully streaming in the mobile phone environment. We have developed a very lightweight video player for use in mobile phone and the related authoring tool for the player. The streaming server has carefully been designed to provide high efficiency, reliability and scalability. Based on a specifically-designed suite of streaming protocol, the server employs an adaptive rate control mechanism which transmits the media packets appropriately into the network according to the change in network bandwidth.Hojung Cha is currently a professor in computer science at Yonsei University, Seoul, Korea. His research interests include multimedia computing system, multimedia communication networks, wireless and mobile communication systems and embedded system software. He received his B.S. and M.S. in computer engineering from Seoul National University, Korea, in 1985 and 1987, respectively. He received his Ph.D. in computer science from the University of Manchester, England, in 1991.Jongmin Lee is a Ph.D. candidiate in computer science at Yonsei University, Seoul, Korea. His research interests include wireless multimedia system, QoS architecture, multimedia communication networks. He received his B.S. and M.S. in computer science from Kwangwoon University in 1999 and 2001, respectively.Jongho Nang is a professor in the Department of Computer Science at Sogang University. He received his B.S. degree from Sogang University, Korea, in 1986 and M.S. and Ph.D. degree from KAIST, in 1988 and in 1992, respectively. His research interests are in the field of multimedia systems, digital video library, and Internet technologies. He is a member of KISS, ACM, and IEEE.Sung-Yong Park is an associate professor in the Department of Computer Science at Sogang University, Seoul, Korea. He received his B.S. degree in computer science from Sogang University, and both the M.S. and Ph.D. degrees in computer science from Syracuse University. From 1987 to 1992, he worked for LG Electronics, Korea, as a research engineer. From 1998 to 1999, he was a research scientist at Telcordia Technologies (formerly Bellcore) where he developed network management software for optical switches. His research interests include high performance distributed computing and systems, operating systems, and multimedia.Jin-Hwan Jeong received the B.S. and M.S. degrees in computer science from Korea University, Seoul, Korea, in 1997, and 1999, respectively. He is currently in Ph.D. course at Korea University. His research interests include video processing for thin devices, multimedia streaming and operating systems.Chuck Yoo received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea and the M.S. and Ph.D. in computer science in University of Michigan. He worked as a researcher in Sun Microsystems Lab. from 1990 to 1995. He joined the Computer Science and Enginnering Department, Korea University, Seoul, Korea in 1995, where he is currently a professor. His research interests include high performance network, multimedia streaming, and operating systems.Jin-Young Choi received the B.S. degree from Seoul National University, Seoul, Korea, in 1982, the M.S. degree from Drexel University in 1986, and the Ph.D. degree from University of Pennsylvania, in 1993. He is currently a professor of Computer Science and Engineering Department, Korea University, Seoul, Korea. His current research interests are in real-time computing, formal methods, programming languages, process algebras, security, software engineering, and protocol engineering.     

一种用于暗域交替式相移掩模设计的自适应版图划分方法

提出了一种新的用于加速130nm以下工艺交替式相移掩模设计流程的版图划分方法,该方法能够自适应调整版图划分的粒度.讨论了消除相位冲突的方法和版图压缩中相位兼容性保持的策略.利用上述算法实现的CAD原型系统经多个工业界例子的测试表明能够有效地适应随版图尺寸而快速增长的相位冲突复杂性,同时提供较好的PSM设计质量,并能满足不同求解精度和加速比的要求.     

A mobile bazaar for wide-area wireless services

We introduce MoB, an infrastructure for collaborative wide-area wireless data services. MoB proposes to change the current model of data services in the following fundamental ways: (1) it decouples infrastructure providers from services providers and enables fine-grained competition, (2) it allows service interactions on arbitrary timescales, and, (3) it promotes flexible composition of these fine-grained service interactions based on user and application needs. At the heart of MoB is an open market architecture in which mobile users can opportunistically trade various services with each other in a flexible manner. In this paper we first describe the overall architecture of MoB including various enablers like user reputation management, incentive management, and accounting services. We next present our experience from both simulations as well as our prototype implementation of MoB in enhancing application performance in multiple different scenarios—file transfers, web browsing, media streaming, and location-enhanced services. This work is supported in part by NSF grants CNS-0520152, CNS-0639434, CNS-0627589 and CNS-0627102. Rajiv Chakravorty received the B.E. degree from Nagpur University, Nagpur, India, in 1997 and the M.Tech. degree form the Indian Institute of Technology, Delhi in 1999. He is working towards the Ph.D. degree at the Computer Laboratory, University of Cambridge, U.K. In 2005 he was a visiting research scholar in the Department of Computer Sciences, University of Wisconsin, Madison. He has worked with Philips Research, ASA Laboratories, Eindhoven, The Netherlands. He also pursued research at ComNets, RWTH-Aachen, Germany. His current interests include mobile and wireless systems, and networking. He is a recipient of DAAD Scholarship Award from Germany, and the Sun Microsystems Scholarship and the Hughes Hall Commonwealth scholarhip from Cambridge Univeristy. Sulabh Agarwal received the B.Tech. degree in Computer Science and Engineering from Indian Institute of Technology, Delhi in 2000, and the M.S. degree in Computer Science from University of Maryland, College Park in 2002. His research interest is in the area of computer networking. Suman Banerjee received the B.Tech. degree in Computer Science and Engineering from Indian Institute of Technology, Kanpur in 1996, and the M.S. and the Ph.D. degrees in Computer Science from University of Maryland, College Park in 1999 and 2003 respectively. He is an Assistant Professor of Computer Sciences at University of Wisconsin-Madison and heads the Wisconsin Wireless and NetworkinG Systems (WiNGS) laboratory. His broad research interests are in the areas of networking and distributed systems with a special focus in the area of wireless and mobile networking systems. Ian Pratt received the Ph.D. in Computer Science from University of Cambridge, Cambridge, U.K. He was elected a Fellow of King’s College, Cambridge, U.K., in 1996. He is a Senior Faculty member at the Computer Loboratory, University of Cambridge, Cambridge, U.K. He is a a leader of the Systems Research Group, where he has been architect of a number of influential projects, including the Desk Area Network workstation, the Cambridge Open Mobile System, the Xen Virtual Machine Monitor, and the XenoServer infrastructure for global computing. His research interests cover a broad range if systems topics, including computer architecture, operating system design, mobile systems, and networking.     

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.As an example of application, a bandgap reference circuit has been considered and the results obtained from simulations have been compared with experimental data. Furthermore, the methodology has been applied to the read path of a complex Flash Memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the validity of the methodology, and the accuracy of both the mismatch model and the simulation flow.