A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

A high-speed ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time

An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circuit techniques. The device is adaptable to modern subnanosecond logic arrays, and, hence, is a member of the Siemens SH 100 family.     

A 30 ns 16K/spl times/1 fully static RAM

A fully static 16K/spl times/1 random access memory (SRAM) with significantly improved speed is discussed. Design innovations using conservative 2.5 /spl mu/m transistors and state-of-the-art double level poly (DLP) scaled NMOS technology were utilized to accomplish 30 ns address and chip select access times with an active power of 550 mW and standby power of 75 mW. A cost effective DLP process was developed using `shared' contacts in the cell. These `shared' contacts utilize second level poly to provide connection between the first poly level and moat, reduced the number of contacts per cell to four. The DPL cell size is 1.6 mil/SUP 2/ (1000 /spl mu/m/SUP 2/) which yields a bar size of 158/spl times/264 mil/SUP 2/ (4.0/spl times/6.7 mm/SUP 2/). In this fully static design a novel architecture was used to power down half of the X-decoders in the active mode using the AO address buffer signals. This technique allowed the use of power saved in the X-decoder to be distributed throughout the circuit to improve overall access times. One of the other major speed improvements came from utilizing column sense amps. The use of the column sense amp improves the overall speed by more than 20 percent. A write cycle of 30 ns has been achieved with a typical write pulse width of 10 ns.     

A 150 ns, 150 mW, 64K dynamic MOS RAM

A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thickness (t/SUB ox/) transistors as active elements. Also, the RAM with a newly designed sense amplifier has successfully been fabricated using only four photo resist masking processes. The access time and power dissipation are 150 ns and 150 mW, respectively, at the cycle time of 400 ns.     

A 4.5 ns access time 1K /spl times/ 4 bit ECL RAM

An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

A fault-tolerant 30 ns/375 mW 16K/spl times/1 NMOS static RAM

A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.     

A 4K/spl times/8 dynamic RAM with self-refresh

A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, counter and multiplexer. A high-speed arbiter resolves simultaneous memory and refresh requests. Redundant rows are used for increased manufacturing yields. Polysilicon fuses are electrically programmed to select redundant rows.     

A 128K word/spl times/8 bit dynamic RAM

A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.     

A 70 ns high density 64K CMOS dynamic RAM

A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.     

A low-power sub 100 ns 256K bit dynamic RAM

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

An 8K/spl times/8 dynamic RAM with self-refresh

The device uses a standard NMOS one-transistor cell and is fabricated with a double polysilicon HMOS technology using polysilicon word lines and folded metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, and refresh counter. A high-speed arbiter resolves conflicts between refresh cycles and memory accesses. A `ready' output is provided to the processor. A multiplexed bus is provided in the array to carry column addresses and also I/O data paths. Another multiplexed bus is used for data lines between the input buffers, write buffers, secondary sense amplifiers, and output buffers. Redundant rows and columns are used for increased manufacturing yield. Polysilicon fuses are electrically programmed to select redundant elements.     

SNOS 1K/spl times/8 static nonvolatile RAM

Using an advanced n-channel, double level polysilicon SNOS technology, a 1K/spl times/8 bit nonvolatile static RAM has been designed. Typical RAM access time is 300 ns, with typical active power dissipation of 300 mW, and standby power of 160 mW. Endurance of 10/SUP 4/ erase/store cycles has been demonstrated. The ability to measure erased and written memory thresholds allows prediction of retention lifetime. For the 8K NVRAM, the minimum retention lifetime is 1 year following a 10 ms erase and store.     

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.     

An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time

An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time, 900 mW power dissipation, and a chip size of 18.3 mm/SUP 2/ has been developed for caches and control memories of high-performance computer systems. The 1K/spl times/4 organisation mode combines the lower cost per bit of a 4K-bit device with the higher memory-module design flexibility of a 1K word unit. The excellent speed performance together with the high packing density have been achieved by using an oxide isolation technology with oxide-walled emitters in conjunction with novel circuit techniques.     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.