A high-performance and scalable multi-core aware software solution for network monitoring

In recent years, the need for high-performance network monitoring tools, which can cope with rapidly increasing network bandwidth, has become vital. A possible solution is to utilize the processing power of multi-core processors that nowadays are available as commercial-off-the-shelf (COTS) hardware. In this paper, we introduce a software solution for wire-speed packet capturing and transmission for TCP/IP networks under Linux operating system, called DashCap. The results of our experimental evaluations show that the proposed solution causes more than two times performance boost for packet capturing in comparison to the existing software solutions under Linux. We have proposed a scalable software architecture for network monitoring tools called DashNMon, which is based on DashCap. Multi-core awareness is a distinguished property of this architecture. Comparing to the existing cluster-based solutions, DashNMon can be used with COTS multi-core processors. In order to evaluate the proposed solutions, we have developed several prototype tools. The results of the experiments carried out using these tools show the scalability and high performance of the network monitoring tools that are based on the proposed architecture. Using the proposed architecture, it is possible to design and implement high-performance multi-threaded network intrusion detection systems (NIDSs) or application-layer firewalls, completely in the user space and with better utilization of the computational resources of multi-processor/multi-core systems.     

A language and programming environment for high-performance parallel computing on heterogeneous networks

An mpC language designed specifically for programming high-performance computations on heterogeneous networks is described. An mpC program explicitly defines an abstract computing network and distributes data, computations, and communications over it. At runtime, the mpC programming environment uses this information and that about the actual network to distribute the processes over the actual network so as to execute the program in the most efficient way. Experience in using mpC for solving problems on local networks consisting of heterogeneous workstations is discussed.     

A class of highly scalable optical crossbar-connectedinterconnection networks (SOCNs) for parallel computing systems

A class of highly scalable interconnect topologies called the Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) is proposed. This proposed class of networks combines the use of tunable Vertical Cavity Surface Emitting Lasers (VCSEL's), Wavelength Division Multiplexing (WDM) and a scalable, hierarchical network architecture to implement large-scale optical crossbar based networks. A free-space and optical waveguide-based crossbar interconnect utilizing tunable VCSEL arrays is proposed for interconnecting processor elements within a local cluster. A similar WDM optical crossbar using optical fibers is proposed for implementing intercluster crossbar links. The combination of the two technologies produces large-scale optical fan-out switches that could be used to implement relatively low cost, large scale, high bandwidth, low latency, fully connected crossbar clusters supporting up to hundreds of processors. An extension of the crossbar network architecture is also proposed that implements a hybrid network architecture that is much more scalable. This could be used to connect thousands of processors in a multiprocessor configuration while maintaining a low latency and high bandwidth. Such an architecture could be very suitable for constructing relatively inexpensive, highly scalable, high bandwidth, and fault-tolerant interconnects for large-scale, massively parallel computer systems. This paper presents a thorough analysis of two example topologies, including a comparison of the two topologies to other popular networks. In addition, an overview of a proposed optical implementation and power budget is presented, along with analysis of proposed media access control protocols and corresponding optical implementation     

Extending Unix for scalable computing

Because it retrieves all instructions and data from a single memory, the von Neumann computer architecture has a fundamental speed limit. The scalable multicomputer architecture, which uses many microprocessors together to solve a single problem and can run at teraflop speeds, may be a solution. While teraflop processor technology is known, the scalable operating and I/O system technology necessary for those speeds are not known. The authors describe how Unix can be extended to scalable computing, permitting teraflop speeds and offering parallel computing to users unfamiliar with parallel programming. They designed this technology into the system software of the Ncube-2, the predecessor to Ncube's announced teraflop parallel computer. The authors describe the system in detail and provide some performance results     

基于太空级 Virtex FPGA的灵活高性能计算平台

采用太空级Virtex FPGA与可重构的系统架构,可满足天基系统对尺寸、重量及功耗的苛刻要求,并缩短设计周期。SEAKR工程公司采用可重构的赛灵思VirtexFPGA创建了灵活的高性能计算平台,用作各种天基系统的核心。该全新计算平台已成功应用于4个太空任务。     

Publish-subscribe for high-performance computing

High-performance computing could significantly benefit from publish-subscribe communication, but current systems don't deliver the kind of performance required by applications in that domain. In response, the authors developed Echo, a high-performance event-delivery middleware designed to scale to the data rates typically found in grid environments. This article provides an overview of Echo, the infrastructure on which it's built, and the techniques used to implement it.     

A scalable high-performance graphics processor: GVIP

The GVIP (geometric and TV image processor) graphics processor, which creates and synthesizes computer graphics and TV images and meets the requirements of multi-media systems, is described. The hardware modules that make up this graphics processor include: a 32-bit embedded RISC processor, a Phong and Gouraud shading processor, a texture mapping processor, a hidden surface removal processor, an HDTV video image processor, a BitBlt processor, an imageprocessing module, and an outline font fill generator. These hardware modules fabricated using 0.8 m CMOS standard cells have been placed in three integrated circuit chips. The total number of gates used for one set of chips is approximately 350000.     

Automated performance prediction for scalable parallel computing

Performance prediction is necessary in order to deal with multi-dimensional performance effects on parallel systems. The compiler-generated analytical model developed in this paper accounts for the effects of cache behavior, CPU execution time and message passing overhead for real programs written in high level data-parallel languages. The performance prediction technique is shown to be effective in analyzing several non-trivial data-parallel applications as the problem size and number of processors vary. We leverage technology from the Maple symbolic manipulation system and the S-PLUS statistical package in order to present users with critical performance information necessary for performance debugging, architectural enhancement and procurement of parallel systems. The usability of these results is improved through specifying confidence intervals as well as predicted execution times for data-parallel applications.     

A parallel computing architecture for high-performance OWL reasoning

The Web Ontology Language (OWL) is a widely used knowledge representation language for describing knowledge in application domains by using classes, properties, and individuals. Ontology classification is an important and widely used service that computes a taxonomy of all classes occurring in an ontology. It can require significant amounts of runtime, but most OWL reasoners do not support any kind of parallel processing. We present a novel thread-level parallel architecture for ontology classification, which is ideally suited for shared-memory SMP servers, but does not rely on locking techniques and thus avoids possible race conditions. We evaluated our prototype implementation with a set of real-world ontologies. Our experiments demonstrate a very good scalability resulting in a speedup that is linear to the number of available cores.     

Python accelerators for high-performance computing

Python became the preferred language for teaching in academia, and it is one of the most popular programming languages for scientific computing. This wide popularity occurs despite the weak performance of the language. This weakness is the motivation that drives the efforts devoted by the Python community to improve the performance of the language. In this article, we are following these efforts while we focus on one specific promised solution that aims to provide high-performance and performance portability for Python applications.     

Rover: scalable location-aware computing

All the components necessary for realizing location-aware computing are available in the marketplace today. What has hindered the widespread deployment of location-based systems is the lack of an integration architecture that scales with user populations. The authors have completed the initial implementation of Rover, a system designed to achieve this sort of integration and to automatically tailor information and services to a mobile user's location. Their studies have validated Rover's underlying software architecture, which achieves system scalability through high-resolution, application-specific resource scheduling at the servers and network. The authors believe that this technology will greatly enhance the user experience in many places, including museums, amusement and theme parks, shopping malls, game fields, offices, and business centers. They designed the system specifically to scale to large user populations and expect its benefits to increase with them.     

A scalable multimedia QoS architecture for ad hoc networks

Communication demands have grown from separate data and voice to integrated multimedia, paving the way to converging fixed, mobile and IP networks. Supporting Multimedia is a challenging task for wireless ad hoc network designers. Multimedia forms high data rate traffic with stringent Quality of Service (QoS) requirements. Wireless ad hoc networks are characterized by frequent topology changes, unreliable wireless channel, network congestion and resource contention. Providing scalable QoS is the most important challenge for multimedia delivery over ad hoc networks. We introduce here a provisioning and routing architecture for ad hoc networks which scales well while provisioning QoS. The proposed architecture is analysed using a mix of HTTP, voice and video streaming applications over 54 Mbps 802.11 g-based ad hoc networks. The architecture is simulated and compared to well-known routing protocols using the OPNET Modeller. The results show that our architecture scales well with increase in the network size, and outperforms well-known routing protocols.     

A sliding window technique for interactive high-performance computing scenarios

Interactive high-performance computing is doubtlessly beneficial for many computational science and engineering applications whenever simulation results should be visually processed in real time, i.e. during the computation process. Nevertheless, interactive HPC entails a lot of new challenges that have to be solved – one of them addressing the fast and efficient data transfer between a simulation back end and visualisation front end, as several gigabytes of data per second are nothing unusual for a simulation running on some (hundred) thousand cores. Here, a new approach based on a sliding window technique is introduced that copes with any bandwidth limitations and allows users to study both large and small scale effects of the simulation results in an interactive fashion.     

A low-overhead networking mechanism for virtualized high-performance computing systems

The use of virtualized parallel and distributed computing systems is rapidly becoming the mainstream due to the significant benefit of high energy-efficiency and low management cost. Processing network operations in a virtual machine, however, incurs a lot of overhead from the arbitration of network devices between virtual machines, inherently by the nature of the virtualized architecture. Since data transfer between server nodes frequently occurs in parallel and distributed computing systems, the high overhead of networking may induce significant performance loss in the overall system. This paper introduces the design and implementation of a novel networking mechanism with low overhead for virtualized server nodes. By sacrificing isolation between virtual machines, which is insignificant in distributed or parallel computing systems, our approach significantly reduces the processing overhead in networking operations by up to 29% of processor load, along with up to 36% of processor cache miss. Furthermore, it improves network bandwidth by up to 8%, especially when transmitting large packets. As a result, our prototype enhances the performance of real-world workloads by up to 12% in our evaluation.     

A loss-event driven scalable fluid simulation method for high-speed networks

Increase of size and bandwidth of computer network posed a research challenge to evaluate proposed TCP/IP protocol and corresponding queuing policies in this scenario. Simulation provides an easier and cheaper method to evaluate TCP proposals and queuing disciplines as compared to experiment with real hardware. In this paper, problem associated with scalability of current simulation method for high-speed network case is discussed. Hence, we present a scalable time-adaptive numerical simulation driven by loss events to represent dynamics of high-speed networks using fluid-based models. The new method uses a loss event to dynamically adjust the size of a time step for a numerical solver which solves a system of differential equations representing dynamics of protocols and nodes’ behaviors. A numerical analysis of the proposed protocol is discussed. A simple simulation of high-speed TCP variants is presented using our method. The simulation results and analysis show that the time-adaptive method reduces computational time while achieving the same accuracy compared to that of a fixed step-size method.     

A scalable correlation aware aggregation strategy for wireless sensor networks

Sensors-to-sink data in wireless sensor networks (WSNs) are typically characterized by correlation along the spatial, semantic, and/or temporal dimensions. Exploiting such correlation when performing data aggregation can result in considerable improvements in the bandwidth and energy performance of WSNs. In this paper, we first identify that most of the existing upstream routing approaches in WSNs can be translated to a correlation-unaware data aggregation structure – the shortest-path tree. Although by using a shortest-path tree, some implicit benefits due to correlation are possible, we show that explicitly constructing a correlation-aware structure can result in considerable performance improvement. Toward this end, we present a simple, scalable and distributed correlation-aware aggregation structure that addresses the practical challenges in the context of aggregation in WSNs. Through simulations and analysis, we evaluate the performance of the proposed approach with centralized and distributed correlation-aware and -unaware structures.     

Overlay networks: A scalable alternative for P2P

Overlay networks create a structured virtual topology above the basic transport protocol level that facilitates deterministic search and guarantees convergence. Overlay networks are evolving into a critical component for self-organizing systems. Here we outline the differences between flooding-style and overlay networks, and offer specific examples of how researchers are applying the latter to problems requiring high-speed, self-organizing network topologies.