A virtual metrology system for semiconductor manufacturing

Nowadays, the semiconductor manufacturing becomes very complex, consisting of hundreds of individual processes. If a faulty wafer is produced in an early stage but detected at the last moment, unnecessary resource consumption is unavoidable. Measuring every wafer’s quality after each process can save resources, but it is unrealistic and impractical because additional measuring processes put in between each pair of contiguous processes significantly increase the total production time. Metrology, as is employed for product quality monitoring tool today, covers only a small fraction of sampled wafers. Virtual metrology (VM), on the other hand, enables to predict every wafer’s metrology measurements based on production equipment data and preceding metrology results. A well established VM system, therefore, can help improve product quality and reduce production cost and cycle time. In this paper, we develop a VM system for an etching process in semiconductor manufacturing based on various data mining techniques. The experimental results show that our VM system can not only predict the metrology measurement accurately, but also detect possible faulty wafers with a reasonable confidence.     

An intelligent virtual metrology system with adaptive update for semiconductor manufacturing

Virtual metrology involves the estimation of metrology values using a prediction model instead of metrological equipment, thereby providing an efficient means for wafer-to-wafer quality control. Because wafer characteristics change over time according to the influence of several factors in the manufacturing process, the prediction model should be suitably updated in view of recent actual metrology results. This gives rise to a trade-off relationship, as more frequent updates result in a higher accuracy for virtual metrology, while also incurring a heavier cost in actual metrology. In this paper, we propose an intelligent virtual metrology system to achieve a superior metrology performance with lower costs. By employing an ensemble of artificial neural networks as the prediction model, the prediction, reliability estimation, and model update are successfully integrated into the proposed virtual metrology system. In this system, actual metrology is only performed for those wafers where the current prediction model cannot perform reliable predictions. When actual metrology is performed, the prediction model is instantly updated to incorporate the results. Consequently, the actual metrology ratio is automatically adjusted according to the corresponding circumstances. We demonstrate the effectiveness of the method through experimental validation on actual datasets.     

Machine learning-based novelty detection for faulty wafer detection in semiconductor manufacturing

Since semiconductor manufacturing consists of hundreds of processes, a faulty wafer detection system, which allows for earlier detection of faulty wafers, is required. statistical process control (SPC) and virtual metrology (VM) have been used to detect faulty wafers. However, there are some limitations in that SPC requires linear, unimodal and single variable data and VM underestimates the deviations of predictors. In this paper, seven different machine learning-based novelty detection methods were employed to detect faulty wafers. The models were trained with Fault Detection and Classification (FDC) data to detect wafers having faulty metrology values. The real world semiconductor manufacturing data collected from a semiconductor fab were tested. Since the real world data have more than 150 input variables, we employed three different dimensionality reduction methods. The experimental results showed a high True Positive Rate (TPR). These results are promising enough to warrant further study.     

Multi-step virtual metrology for semiconductor manufacturing: A multilevel and regularization methods-based approach

In semiconductor manufacturing, wafer quality control strongly relies on product monitoring and physical metrology. However, the involved metrology operations, generally performed by means of scanning electron microscopes, are particularly cost-intensive and time-consuming. For this reason, in common practice a small subset only of a productive lot is measured at the metrology stations and it is devoted to represent the entire lot. Virtual Metrology (VM) methodologies are used to obtain reliable predictions of metrology results at process time, without actually performing physical measurements. This goal is usually achieved by means of statistical models and by linking process data and context information to target measurements. Since semiconductor manufacturing processes involve a high number of sequential operations, it is reasonable to assume that the quality features of a given wafer (such as layer thickness and critical dimensions) depend on the whole processing and not on the last step before measurement only. In this paper, we investigate the possibilities to enhance VM prediction accuracy by exploiting the knowledge collected in the previous process steps. We present two different schemes of multi-step VM, along with dataset preparation indications. Special emphasis is placed on regression techniques capable of handling high-dimensional input spaces. The proposed multi-step approaches are tested on industrial production data.     

Virtual metrology and feedback control for semiconductor manufacturing processes using recursive partial least squares

Virtual metrology (VM) is the prediction of metrology variables (either measurable or non-measurable) using process state and product information. In the past few years VM has been proposed as a method to augment existing metrology and has the potential to be used in control schemes for improved process control in terms of both accuracy and speed. In this paper, we propose a VM based approach for process control of semiconductor manufacturing processes on a wafer-to-wafer (W2W) basis. VM is realized by utilizing the pre-process metrology data and more importantly the process data from the underlying tools that is generally collected in real-time for fault detection (FD) purposes. The approach is developed for a multi-input multi-output (MIMO) process that may experience metrology delays, consistent process drifts, and sudden shifts in process drifts. The partial least squares (PLS) modeling technique is applied in a novel way to derive a linear regression model for the underlying process, suitable for VM purposes. A recursive moving-window approach is developed to update the VM module whenever metrology data is available. The VM data is then utilized to develop a W2W process control capability using a common run-to-run control technique. The proposed approach is applied to a simulated MIMO process and the results show considerable improvement in wafer quality as compared to other control solutions that only use lot-to-lot metrology information.     

Wafer-level reliability characterization for wafer-level-packaged microbolometer with ultrasmall array size

For the development of a small and low-cost microbolometer, wafer-level reliability characterization techniques for vacuum-level packaged wafers are introduced. Amorphous-silicon-based microbolometer-type vacuum sensors fabricated on an 8-inch wafer are bonded with a cap wafer by using an Au–Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity at the wafer level. For a packaged wafer with a membrane thickness below 100 μm, it is possible to determine the hermeticity via a screening test performed using an optical detector. An integrated vacuum sensor having the same structure as a bolometer pixel shows a vacuum level below 100 mTorr. All steps from the packaging process to the fine hermeticity test are implemented at the wafer level to verify that high-volume and low-cost production of the microbolometer is possible.     

A virtual metrology model based on recursive canonical variate analysis with applications to sputtering process

In data driven process monitoring, soft-sensor, or virtual metrology (VM) model is often employed to predict product's quality variables using sensor variables of the manufacturing process. Partial least squares (PLS) are commonly used to achieve this purpose. However, PLS seeks the direction of maximum co-variation between process variables and quality variables. Hence, a PLS model may include the directions representing variations in the process sensor variables that are irrelevant to predicting quality variables. In this case, when direction of sensor variables’ variations most influential to quality variables is nearly orthogonal to direction of largest process variations, a PLS model will lack generalization capability. In contrast to PLS, canonical variate analysis (CVA) identifies a set of basis vector pairs which would maximize the correlation between input and output. Thus, it may uncover complex relationships that reflect the structure between quality variables and process sensor variables. In this work, an adaptive VM based on recursive CVA (RCVA) is proposed. Case study on a numerical example demonstrates the capability of CVA-based VM model compared to PLS-based VM model. Superiority of the proposed model is also presented when it applied to an industrial sputtering process.     

Microdisplay wafer‐flatness metrology by optical interferometry

Abstract— We report a microdisplay wafer‐flatness metrology technique based on digital high‐pass filtering of topography data obtained from a commercial optical interferometer. This technique discriminates against both wafer‐scale bow/warp and pixel‐scale roughness to reveal die‐scale flatness variations that are the most relevant to microdisplay gap uniformity. We report flatness measurements of a variety of live and test silicon wafers supporting VLSI microdisplay circuitry, and show how these measurements correlate with the performance of liquid‐crystal microdisplays assembled from similar wafers. The technique is sensitive to cross‐die flatness variations as small as 25 nm in the presence of wafer bow of tens of microns. The wafer flatness variations that make the greatest contribution to liquid‐crystal cell‐gap non‐uniformity arise from interactions between the chemical mechanical planarization (CMP) process and the VLSI circuit layout. Our metrology technique can help the VLSI designer optimize microdisplay layout, and provides an objective flatness specification for wafers purchased from third‐party foundries.     

Virtual metrology modeling of time-dependent spectroscopic signals by a fused lasso algorithm

This paper proposes a fused lasso model to identify significant features in the spectroscopic signals obtained from a semiconductor manufacturing process, and to construct a reliable virtual metrology (VM) model. Analysis of spectroscopic signals involves combinations of multiple samples collected over time, each with a vast number of highly correlated features. This leads to enormous amounts of data, which is a challenge even for modern-day computers to handle. To simplify such complex spectroscopic signals, dimension reduction is critical. The fused lasso is a regularized regression method that performs automatic variable selection for the predictive modeling of highly correlated datasets such as those of spectroscopic signals. Furthermore, the fused lasso is especially useful for analyzing high-dimensional data in which the features exhibit a natural order, as is the case in spectroscopic signals. In this paper, we conducted an experimental study to demonstrate the usefulness of a fused lasso-based VM model and compared it with other VM models based on the lasso and elastic-net models. The results showed that the VM model constructed with features selected by the fused lasso algorithm yields more accurate and robust predictions than the lasso- and elastic net-based VM models. To the best of our knowledge, ours is the first attempt to apply a fused lasso to VM modeling.     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing

Semiconductor manufacturing processes are very long and complex, needing several hundreds of individual steps to produce the final product (chip). In this context, the early detection of process excursions or product defects is very important to avoid massive potential losses. Metrology is thus a key step in the fabrication line. Whereas a 100 % inspection rate would be ideal in theory, the cost of the metrology devices and cycle time losses due to these measurements would completely inhibit such an approach. On another hand, the skipping of some measurements is risky for quality assurance and processing machine reliability. The purpose is to define an optimized quality control plan that reduces the required capacity of control while maintaining enough trust in quality controls. The method adopted by this research is to employ a multi-objective genetic algorithm to define the optimized control plan able to reduce the used metrology capacity without increasing risk level. Early results based on one month of real historical data computation reveal a possible reallocation of controls with a decrease by more than 15 % of metrology capacity while also reducing the risk level on the processing machine (expressed by the wafer at risk (\(W\!@\!R\))) by 30 %.     

Intelligent maintenance prediction system for LED wafer testing machine

Achieving high quality production of light-emitting diode (LED) wafers requires robust monitoring and the use of a stable test machine. In many factories, production continues 24 h a day. Stopping the manufacturing process at a factory is often difficult. Therefore, reducing inspection time and ensuring the stability of test machines are important. Traditionally, LED wafer factories examine their test machines during periodic maintenance. Standard lamp adjustments are performed to ensure their accuracy. This process interrupts the manufacturing process and requires extra manpower. It reduces productivity and increases production cost. Additionally, the accurate assessment of the aging of the components of the machine requires an experienced engineer. Correctly timing the maintenance and replacing the aging components of the LED wafer test machine are important. This work performed feature extraction to identify the working attributes of an LED wafer test machine. The intelligent maintenance prediction system then uses the radial basis function neural network and variability of the working attributes to predict the maintenance times and aging of the LED wafer test machines. Experimental results reveal that the accuracy of proposed system in predicting maintenance times exceeds 98 %.     

Defective wafer detection using a denoising autoencoder for semiconductor manufacturing processes

Defective wafer detection is essential to avoid loss of yield due to process abnormalities in semiconductor manufacturing. For most complex processes in semiconductor manufacturing, various sensors are installed on equipment to capture process information and equipment conditions, including pressure, gas flow, temperature, and power. Because defective wafers are rare in current practice, supervised learning methods usually perform poorly as there are not enough defective wafers for fault detection (FD). The existing methods of anomaly detection often rely on linear excursion detection, such as principal component analysis (PCA), k-nearest neighbor (kNN) classifier, or manual inspection of equipment sensor data. However, conventional methods of observing equipment sensor readings directly often cannot identify the critical features or statistics for detection of defective wafers. To bridge the gap between research-based knowledge and semiconductor practice, this paper proposes an anomaly detection method that uses a denoise autoencoder (DAE) to learn a main representation of normal wafers from equipment sensor readings and serve as the one-class classification model. Typically, the maximum reconstruction error (MaxRE) is used as a threshold to differentiate between normal and defective wafers. However, the threshold by MaxRE usually yields a high false positive rate of normal wafers due to the outliers in an imbalanced data set. To resolve this difficulty, the Hampel identifier, a robust method of outlier detection, is adopted to determine a new threshold for detecting defective wafers, called MaxRE without outlier (MaxREwoo). The proposed method is illustrated using an empirical study based on the real data of a wafer fabrication. Based on the experimental results, the proposed DAE shows great promise as a viable solution for on-line FD in semiconductor manufacturing.     

M-TEST: A test chip for MEMS material property measurement usingelectrostatically actuated test structures

A set of electrostatically actuated microelectromechanical test structures is presented that meets the emerging need for microelectromechanical systems (MEMS) process monitoring and material property measurement at the wafer level during both process development and manufacturing. When implemented as a test chip or drop-in pattern for MEMS processes, M-Test becomes analogous to the electrical MOSFET test structures (often called E-Test) used for extraction of MOS device parameters. The principle of M-Test is the electrostatic pull-in of three sets of test structures [cantilever beams (CB's), fixed-fixed beams (FB's), and clamped circular diaphragms (CD's)] followed by the extraction of two intermediate quantities (the S and B parameters) that depend on the product of material properties and test structure geometry. The S and B parameters give a direct measure of the process uniformity across an individual wafer and process repeatability between wafers and lots. The extraction of material properties (e.g., Young's modulus, plate modulus, and residual stress) from these S and B parameters is then accomplished using geometric metrology data. Experimental demonstration of M-Test is presented using results from MIT's dielectrically isolated wafer-bonded silicon process. This yielded silicon plate modulus results which agreed with literature values to within ±4%. Guidelines for adapting the method to other MEMS process technologies are presented     

Real-time virtual metrology and control for plasma etch

Plasma etch is a semiconductor manufacturing process during which material is removed from the surface of semiconducting wafers, typically made of silicon, using gases in plasma form. A host of chemical and electrical complexities make the etch process notoriously difficult to model and troublesome to control. This work demonstrates the use of a real-time model predictive control scheme to control plasma electron density and plasma etch rate in the presence of disturbances to the ground path of the chamber. Virtual metrology (VM) models, using plasma impedance measurements, are used to estimate the plasma electron density and plasma etch rate in real time for control, eliminating the requirement for invasive measurements. The virtual metrology and control schemes exhibit fast set-point tracking and disturbance rejection capabilities. Etch rate can be controlled to within 1% of the desired value. Such control represents a significant improvement over open-loop operation of etch tools, where variances in etch rate of up to 5% can be observed during production processes due to disturbances in tool state and material properties.     

基于局部与非局部线性判别分析和高斯混合模型动态集成的晶圆表面缺陷探测与识别

在复杂的半导体制造过程中,晶圆生产经过薄膜沉积、蚀刻、抛光等多项复杂的工序,制造过程中的异常波动都可能导致晶圆缺陷产生.晶圆表面的缺陷模式通常反映了半导体制造过程的各种异常问题,生产线上通过探测和识别晶圆表面缺陷,可及时判断制造过程故障源并进行在线调整,降低晶圆成品率损失.本文提出了基于一种流形学习算法与高斯混合模型动态集成的晶圆表面缺陷在线探测与识别模型.首先该模型开发了一种新型流形学习算法——局部与非局部线性判别分析法(Local and nonlocal linear discriminant analysis, LNLDA),通过融合数据局部/非局部信息以及局部/非局部惩罚信息,有效地提取高维晶圆特征数据的内在流形结构信息,以最大化数据不同簇样本的低维映射距离,保持特征数据中相同簇的低维几何结构.针对线上晶圆缺陷产生的随机性和复杂性,该模型对每种晶圆缺陷模式构建相应的高斯混合模型(Gaussian mixture model, GMM),提出了基于高斯混合模型动态集成的晶圆缺陷在线探测与识别方法.本文提出的模型成功地应用到实际半导体制造过程的晶圆表面缺陷在线探测与识别,在WM-811K晶圆数据库的实验结果验证了该模型的有效性与实用性.     

Application of an Ordinal Optimization Algorithm to the Wafer Testing Process

In this correspondence, we have formulated a stochastic optimization problem to find the optimal threshold values to reduce the overkills of dies under a tolerable retest level in wafer testing process. The problem is a hard optimization problem with a huge solution space. We propose an ordinal optimization theory-based two-level algorithm to solve for a vector of good enough threshold values and compare with those obtained by others using a set of 521 real test wafers. The test results confirm the feature of controlling the retest level in our formulation, and the pairs of overkills and retests resulted from our approach are almost Pareto optimal. In addition, our approach spends only 6.05 min in total in a Pentium IV personal computer to obtain the good enough threshold values     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

星载软件可靠性模型应用研究及实践

为定量评估软件的可靠性指标,介绍了利用软件可靠性模型评估软件可靠性的过程和方法;针对某星载嵌入式软件的失效趋势,根据模型的选择原则和方法,以及模型的预测质量的对比,最终选择了指数模型作为可靠性评估模型。对该软件在轨运行情况进行了可靠性评估,开展了基于该软件可靠性测试数据的可靠性评估,评估结果给出了该软件的可靠性水平。     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.