STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET’s

Grooved gate structure Metal-Oxide-Semiconductor(MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region,for it can suppress hot carrier effect and short channel effect deeply.Based on the hydrodynamic energy transoprt model,using two-dimensional device simulator Medici,the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel Mosfet‘s is studied and compared with that of counterpart conventional planar device in this paper.The examined structure parameters include negative junction depth,conventinal planar device in this paper.The examined structure parameters include negative junction depth,concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device.With the increase of concave corner,the hot carrier effect in groovd gate MOSFET decreases sharply,and with the reducing of effective channel length,the hot carrier effect becomes large.     

槽栅NMOSFET结构与性能仿真

基于流体动力学能量输运模型 ,利用二维器件模拟器 MEDICI对深亚微米槽栅 NMOSFET器件的结构参数 ,如结深、凹槽拐角及沟道长度等对器件性能的影响进行了仿真研究 ,并与相应的常规平面器件特性进行了对比 .研究表明在深亚微米范围内 ,槽栅器件能够很好地抑制短沟道效应和热载流子效应 ,但电流驱动能力较平面器件小 ,且器件性能受凹槽拐角和沟道长度的影响较显著     

深亚微米槽栅NMOSFET结构参数对其抗热载流子特性的影响

基于流体动力学能量输运模型和幸运热载流子模型,用二维器件仿真软件Medici对深亚微米槽栅NMOSFET的结构参数,如沟道长度、槽栅凹槽拐角角度、漏源结深等,对器件抗热载流子特性的影响进行了模拟分析,并与常规平面器件的相应特性进行了比较.结果表明即使在深亚微米范围,槽栅器件也能很好地抑制热载流子效应,且其抗热载流子特性受凹槽拐角和沟道长度的影响较显著,同时对所得结果从内部物理机制上进行了分析解释.     

槽栅NMOSFET结构与性能仿真

基于流体动力学能量输运模型,利用二维器件模拟器MEDICI对深亚微米槽栅NMOSFET器件的结构参数,如结深、凹槽拐角及沟道长度等对器件性能的影响进行了仿真研究,并与相应的常规平面器件特性进行了对比.研究表明在深亚微米范围内,槽栅器件能够很好地抑制短沟道效应和热载流子效应,但电流驱动能力较平面器件小,且器件性能受凹槽拐角和沟道长度的影响较显著.     

深亚微米槽栅PMOSFET几何结构参数对抗热载流子特性的影响

基于流体动力学能量输运模型,利用二维仿真软件Medici对深亚微米槽栅PMOS器件的几何结构参数,如:沟道长度、凹槽拐角、凹槽深度和漏源结深导致的负结深对器件抗热载流子特性的影响进行了研究。并从器件内部物理机理上对研究结果进行了解释。研究发现,在深亚微米和超深亚微米区域,槽栅器件能够很好地抑制热载流子效应,且随着凹槽拐角、负结深的增大,器件的抗热载流子能力增强。这主要是因为这些结构参数影响了电场在槽栅MOS器件的分布和拐角效应,从而影响了载流子的运动并使器件的热载流子效应发生变化。     

深亚微米槽栅PMOSFET结构参数对其抗热载流子效应和短沟道抑制作用的影响

基于流体动力学能量输运模型 ,利用二维仿真软件 Medici对深亚微米槽栅 PMOS器件的结构参数 ,如凹槽拐角、负结深、沟道和衬底掺杂浓度对器件抗热载流子特性和短沟道效应抑制作用的影响进行了研究 .并从器件内部物理机理上对研究结果进行了解释 .研究发现 ,随着凹槽拐角、负结深的增大和沟道杂质浓度的提高 ,器件的抗热载流子能力增强 ,阈值电压升高 ,对短沟道效应的抑制作用增强 .而随着衬底掺杂浓度的提高 ,虽然器件的短沟道抑制能力增强 ,但抗热载流子性能降低     

凹槽拐角对深亚微米槽栅PMOSFET特性的影响

为优化槽栅器件结构 ,提高槽栅 MOSFET的性能和可靠性 ,文中用器件仿真软件对凹槽拐角对深亚微米槽栅 PMOSFET的特性影响进行了研究。研究结果表明凹槽拐角强烈影响器件的特性 :随着凹槽拐角的增大 ,阈值电压上升 ,电流驱动能力提高 ,而热载流子效应大大减弱 ,抗热载流子性能增强 ,热载流子可靠性获得提高 ;但凹槽拐角过大时 (例如 90°) ,器件特性变化有所不同     

杂质浓度对槽栅PMOSFET抗热载流子特性的影响

基于流体动力学能量输运模型 ,利用二维仿真软件 Medici研究了深亚微米槽栅 PMOS器件衬底和沟道掺杂浓度对器件抗热载流子特性的影响 ,并从器件内部物理机理上对研究结果进行了解释。研究发现 ,随着沟道杂质浓度的提高 ,器件的抗热载流子能力增强 ;而随着衬底掺杂浓度的提高 ,器件的抗热载流子性能降低。这主要是因为这些结构参数影响了电场在槽栅 MOS器件内的分布和拐角效应 ,从而影响了载流子的运动并使器件的热载流子效应发生变化     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

深亚微米槽栅PMOS结构对抗热载流子效应的影响

基于流体动力学能量输运模型 ,利用二维仿真软件 MEDICI对深亚微米槽栅 PMOS器件的结构参数 ,如凹槽拐角、负结深、沟道和衬底掺杂浓度对器件抗热载流子特性的影响进行了研究 ,并从器件物理机制上对研究结果进行了解释。研究发现 ,随着凹槽拐角、负结深的增大和沟道杂质浓度的提高 ,器件的抗热载流子能力增强。而随着衬底掺杂浓度的提高 ,器件的抗热载流子性能降低。结构参数影响了电场在槽栅 MOS器件的分布和拐角效应 ,从而影响了载流子的运动并使器件的热载流子效应发生变化。     

Simulation of sub-0.1-μm MOSFETs with completely suppressedshort-channel effect

MOSFETs in the sub-0.1-μm regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 μm or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping     

新型槽栅nMOSFET热载流子效应的模拟研究

应用二维器件仿真程序 PISCES- ,对槽栅结构和平面结构器件的特性进行了模拟比较 ,讨论了槽栅结构 MOSFET的沟道电场特征及其对热载流子效应的影响。槽栅结构对抑制短沟道效应和抗热载流子效应是十分有利的 ,而此种结构对热载流子的敏感 ,使器件的亚阈值特性、输出特性变化较大     

异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*

本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型．并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究．该模型中考虑以下参数：金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分．结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL．同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率．此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高．数值模拟器ISE验证了该模型的正确性．     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.     

Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emission

Channel electric field reduction using an n⁺-n^-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n^-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.     

一种非对称双栅应变硅HALO掺杂沟道MOSFET阈值电压解析模型

提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性.     

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.     

施主型界面态引起深亚微米槽栅PMOS特性的退化

基于流体动力学能量输运模型 ,对沟道杂质浓度不同的槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 ,并与受主型界面态的影响进行了对比 .研究结果表明同样浓度的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且 N型施主界面态密度对器件特性的影响远大于 P型界面态 ,N型施主界面态引起器件特性的退化趋势与 P型受主界面态相似 ,而 P型施主界面态则与 N型受主界面态相似 .沟道杂质浓度不同 ,界面态引起的器件特性的退化则不同     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。