Design and Measurement of a CT $DeltaSigma$ ADC With Switched-Capacitor Switched-Resistor Feedback

The performance of traditional continuous-time (CT) delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. A theoretical investigation is carried out which provides new insight into the synthesis of switched-capacitor with switched series resistor (SCSR) DACs with a specified reduction of the pulse-width jitter sensitivity and minimal power consumption and complexity. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz, second order, low-pass, 1-bit, CT DeltaSigma modulator with SCSR feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process. An SNR of 66.4 dB and an SNDR of 62.4 dB were measured in a 1.92 MHz bandwidth. The sensitivity to wideband clock phase noise was reduced by 30 dB compared to a traditional switched-current (SI) return-to-zero (RZ) DAC.     

A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 $mu$ m CMOS

In this letter, a multi-gigahertz phase-locked loop (PLL) with a compact low-pass filter is presented. By using a novel dual-path control in the PLL architecture, the capacitance in the loop filter can be effectively reduced for high-level integration while maintaining the required loop bandwidth. Consequently, the noise resulted from off-chip components is therefore eliminated, leading to lower timing jitter at the PLL output waveforms. In addition, the timing jitter is further suppressed due to the use of decomposed phase and frequency detection. Based on the proposed techniques, a 10 GHz PLL is implemented in 0.18 mum CMOS for demonstration. Consuming a dc power of 113 mW from a 1.8 V supply, the fabricated circuit exhibits a locking range from 10.1 to 11 GHz. At an output frequency of 10.3 GHz, the measured peak-to-peak and rms jitter are 3.78 and 0.44 ps, respectively.     

A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- $muhbox{m}$ LTPS-TFT Technology

A phase-locked loop (PLL) with self-calibrated charge pumps (CPs) has been fabricated in a 3- $muhbox{m}$ low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. A voltage scaler and self-calibrated CPs are used to reduce the static phase error, reference spur, and jitter of an LTPS-TFT PLL. This PLL operates from 5.6 to 10.5 MHz at a supply of 8.4 V. Its area is 18.9 $hbox{mm}^{2}$, and it consumes 7.81 mW at 10.5 MHz. The measured static phase error without and with calibration is 80 and 6.56 ns, respectively, at 10.5 MHz. The measured peak-to-peak jitter without and with calibration is 3.573 and 2.834 ns, respectively. The measured reference spur is $-$26.04 and $-$ 30.2 dBc without and with calibration, respectively. The measured maximal locked time is 1.75 ms.      

A 64 $times$ 64-Pixel CMOS Test Chip for the Development of Large-Format Ultra-High-Speed Snapshot Imagers

A 64 $times$ 64-pixel test circuit was designed and fabricated in 0.18-$mu{hbox {m}}$ CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit performance, test structures are periodically located throughout the 64 $times$ 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than $pm$ 3 ps and jitter that is less than $pm$1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.      

A 7 ps Jitter 0.053 mm $^{2}$ Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC

This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 $mu$ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7$~$ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm$^{2}$.      

A $Delta{-}Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A triangular-modulated spread-spectrum clock generator using a$Delta{-}Sigma$-modulated fractional-$N$ phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased $Delta{-}Sigma$ operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of $pm$0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies $950times850 {rm mu}{rm m}^{2}$ in 0.18-${rm mu}{rm m}$ CMOS process and consumes 36 mW.      

2$,times,$ 2 InP Optical Switching Matrix Based on Carrier-Induced Effects for 1.55-$mu$m Applications

This letter demonstrates a 2times2 low optical crosstalk and low power consumption switching matrix device based on carrier-induced effects on an InP substrate. The matrix device comprises two digital optical switches (DOSs) with a wide multimode Y-junction associated with a sinusoidal passive integrated optical circuit with an optimized X-crossing. The passive structure was designed using a two-dimensional beam propagation method (BPM) and the entire InP-InGaAsP-InP DOS was designed using a semivectorial three-dimensional BPM. The fabricated 2times2 InP switching matrix heterostructure with lambdag=1.3 mum exhibits optical crosstalk as low as -30.5 dB for drive current of 52 mA at 1.55-mum wavelength. Maximum crosstalk change of 4 dB is measured under optical polarization variation.     

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

$L$ -Band Polarization-Independent Reflective SOA for WDM-PON Applications

An $L$-band polarization-independent reflective semiconductor optical amplifier (RSOA) is demonstrated for the first time. Optical gain of greater than 21 dB and gain flatness better than 4 dB is achieved over the $L$-band. The polarization-dependent gain estimated using a polarization resolved spectrum is less than 1 dB over the $L$-band. The measured output saturation power is $-$1.0 dBm and the noise figure (NF) is 10 dB for the packaged device. The 3-dB frequency bandwidth for the device is 1.3 GHz making it suitable for 1.25-Gb/s modulated wavelength-division-multiplexed passive optical network networks. Further, the saturation power and the NF of the RSOA were compared with an SOA of identical length.      

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

3-GHz Silicon Photodiodes Integrated in a 0.18-$mu$m CMOS Technology

A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal–oxide–semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of $70times 70 mu$m $^{2}$ fabricated in a 0.18- $mu$m epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode.      

Analysis of Clock-Jitter Effects in Continuous-Time $Delta Sigma $ Modulators Using Discrete-Time Models

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) $Delta Sigma $ modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT $Delta Sigma $ modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the $Delta Sigma $ modulator.      

Studies of high-speed metal-semiconductor-metal photodetector witha GaAs/AlGaAs/GaAs heterostructure

A GaAs/AlGaAs/GaAs heterostructure metal-semiconductor-metal photodetector (HMSM) with an active area of 100 μm×100 μm was developed and studied. The measured risetime of the device is 30 ps. The measured falltime is as short as 23 ps. The observed ultrafast response is attributed to the reduction of both the carrier transit time and the device capacitance due to the incorporation of the AlGaAs barrier layer. The HMSM is found to have a smaller saturation capacitance and saturates at a much lower bias voltage in comparison with the conventional MSM photodetector (CMSM). At a bias of 10 V, the full width at half maximum (FWHM) of the temporal response of the HMSM is more than 20% smaller than that of the CMSM. In addition, it is found that the peak impulse response for the HMSM is substantially larger than that of the CMSM under the same operation condition. Two-dimensional and equivalent circuit analyses were carried out to interpret the observed phenomena and to provide insight into the underlying physics     

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

A Novel 4$, times ,$4 Optical Switch Using an Anisotropically Etched Micromirror Array and a Bistable Mini-Actuator Array

This letter presents a novel approach to realize a 4 times 4 optical switch. The optical switch consists of a micromachined silicon micromirror array and a bistable mini-actuator array. The micromirror array, which comprises vertical mirrors, cantilevers, and trenches, can be monolithically fabricated by a simple anisotropic silicon etching process in high precision and high yield. The mini-actuator array consists of 16 commercially available bistable actuators integrated with L-shape arms. The advantages of this approach include high precision, easy alignment, high fabrication yield, and low cost. Because of bistable actuation, the power consumption is very low and thus the temperature elevation of a working device is less than 0.3 K. The measured insertion losses of the four channels are between - 1.6 and - 2.3 dB. The measured crosstalk is less than -60 dB, and the measured switching time is about 13 ms.     

In-Vitro and In-Vivo Trans-Scalp Evaluation of an Intracranial Pressure Implant at 2.4 GHz

Elevation of intracranial pressure is one of the most important issues in neurosurgery and neurology in clinical practice. The prevalent techniques for measuring intracranial pressure require equipments that are wired, restricted to a hospital environment, and cause patient discomfort. A novel method for measuring the intracranial pressure is described. A wireless completely implantable device, operating at an industrial-scientific-medical band of 2.4 GHz, has been developed and tested. In-vitro and in-vivo evaluations are described to demonstrate the feasibility of microwave pressure monitoring through scalp, device integrity over a long period of time, and repeatability of pressure measurements. A distinction between an epidural and sub-dural pressure monitoring techniques is also described. Histo-pathological results obtained upon a long-term device implantation favor the utilization of the sub-dural pressure monitoring method. On the other hand, in-vivo studies illustrate a maximum pressure reading error of 0.8 mm middot Hg obtained for a sub-dural device with a capacitive microelectromechanical system sensor compared to 2 mm middot Hg obtained for an epidural device with a piezoresistive sensor.     

Communication Limits Due to Photon Detector Jitter

Detector jitter, the random delay from the time a photon is incident on a single-photon-counting detector (SPD) to the time an electrical pulse is produced in response to that photon, is characterized for a number of SPDs. The jitter is modeled as a weighted sum of Gaussians. The performance in detector jitter is measured by determining the capacity of a communications channel utilizing a given detector. It is observed that the loss, measured as the ratio of the signal power required to achieve a specified capacity in the presence of jitter to that in the absence of jitter, goes as the square of the normalized jitter standard deviation (the standard deviation of the jitter in slotwidths). The loss is small when the normalized jitter is less than one, and becomes significant beyond that point. This loss must be taken into account when evaluating detectors for very high throughput channels.     

Frequency response of InP/InGaAsP/InGaAs avalanche photodiodes with separate absorption "grading" and multiplication regions

We have measured the frequency response of InP/ InGaAsP/InGaAs photodiodes with separate absorption, "grading," and multiplication regions (SAGM-APD's) for a wide range (2 leq M_{0} leq 35) of dc gains. The results are explained in terms of a theoretical model which incorporates the transit time of carriers through the depletion region, the RC time constant, the accumulation of holes at the valence band discontinuity of the heterojunction interfaces, and the gain-bandwidth limit.     

Fiber Inline Core–Cladding-Mode Mach–Zehnder Interferometer Fabricated by Two-Point CO$_{2}$ Laser Irradiations

We report a fiber inline Mach–Zehnder-type core–cladding-mode interferometer fabricated by two-point CO$_{2}$ laser irradiations on a single-mode fiber. The laser irradiations caused efficient light coupling from the core mode to the lower order cladding modes and vise versa. High-quality interference spectra with a fringe visibility of about 20 dB were observed for four different interferometer lengths (5, 10, 20, and 40 mm). The temperature sensitivity of the device with a length of 5 mm was measured to be 0.0817 nm/$^{circ}$C. The sensitivity for refractive index measurement of the device was comparable with a long-period fiber grating of LP$_{04}$ cladding mode.      

Transit Time of Junction Transistors at High Bias Currents†

A study is made of the behaviour of the small-signal base transit time of a transistor at high bias current levels, where increase of transit time occurs due to collector depletion layer contraction in combination with high level injection effects in the base. Computation of theoretical current dependence of transit time is carried out for devices of single-diffused base grading with alloyed emitter and collector junctions. A physical model of the devices, involving exponential base impurity density grading, is used as a basis of analysis. The physical parameters of this model are determined specifically for the transistor samples under study by interpretation of measured terminal properties under low-level injection conditions. Very close agreement between measured and computed dependence of base transit time on d. c. bias current is obtained, subject to appropriate allowance, in analysis, for variation of the operating temperature of the device with d. c. bias condition.