Recessed polysilicon encapsulated local oxidation

Local oxidation of silicon (LOCOS) is the most commonly used isolation technology in silicon integrated circuits. The inherently large field oxide encroachment associated with LOCOS severely limits scalability. Recessed polysilicon encapsulated local oxidation (recessed PELOX) is demonstrated to achieve both low encroachment and increased field oxide recess. These benefits are obtained without sacrificing process simplicity or defectivity as evidenced by excellent gate oxide and diode quality     

Selective polysilicon oxidation technology for VLSI isolation

Field isolation technology is described for small geometry VLSI's in which selective polysilicon oxidation is essential. The technology, also known as SEPOX, offers resist pattern reproducibility in field oxide, while maintaining crystal perfection in the substrate. By a series of experiments, high oxide reliability resulting from a white ribbon-free nature, long lifetime from C-T measurement, and small leakage currents in a reverse biased p-n junction were obtained, as well as a small geometry structure. The feasibility of this technology for MOS LSI's were examined in a 3-µm rule memory chip, and a reasonable yield and reliability were obtained. The physical limitations of SEPOX were also considered and submicrometer capability was confirmed.     

Sealed-interface local oxidation technology

A new regime of local oxidation, dubbed SILO for Sealed-Interface Local Oxidation, is explored. In SILO processing, a film of silicon nitride is in intimate contact with the silicon surface. The ubiquitous native oxide is effectively eliminated by using nitrogen ion implantation into silicon or plasma-enhanced nitridation to form a "sealing film" of approximately 100 Å in thickness. The oxidation rate of both types of films is characterized and found to be nearly equivalent. A 100-Å film can mask the growth 0f 7000 Å of oxide in wet oxygen at 950° C. With a sealed interface it is found that the usual "bird's beak" formation is completely suppressed in local oxidation. An approximate theoretical analysis shows that even a very thin interfacial oxide, acting as a lateral diffusion path for the oxidant species, can lead to a significant bird's beak. With a sealed interface using a 90-Å film, the thick-oxide to bare-silicon transition region is chisel shaped, with approximately 45° slopes. The transition region is even more abrupt if a conventional LPCVD nitride film is deposited on the sealing film before patterning. However, for total nitride thicknesses greater than about 300 Å, defects are generated along the pattern edges aligned in [110] directions. Crystal damage generated during oxidation is found to be due to the intrinsic stress in the LPCVD nitride film. Argon-ion implantation into LPCVD nitride is found to be effective in reducing the defect density. A defect-free abrupt profile is produced by combining SILO with a nitride-oxide sandwich.     

An advanced model for dopant diffusion in polysilicon

A two-dimensional simulation model for dopant diffusion in polysilicon has been developed, which includes dopant clustering in grain interiors as well as in grain boundaries. The grain growth model is coupled with the diffusion coefficient of the dopants and the process temperature based on thermodynamic concepts. For high dose implantation cases the trapping/emission mechanism between grain interiors and grain boundaries and the grain growth are the major effects during thermal treatment processes. The polysilicon grains itself are assumed to be tiny squares, growing from initial size. In order to handle nonplanar semiconductor structures, we use a transformation method for the simulation area as well as for the PDEs.<>     

Field emission characteristics of an oxidized porous polysilicon field emitter using the electrochemical oxidation process

The field emission characteristics of an oxidized porous polysilicon (OPPS) were investigated with Pt/Ti multilayer electrode using the electrochemical oxidation (ECO) process. A Pt/Ti multilayer electrode, using ECO, showed highly efficient and stable electron emission characteristics; moreover, it can be applied to large area of a glass substrate with a low temperature process. Electron emission characteristics were improved with O₂ annealing at 600 °C after the ECO process. It was found that forming a high quality oxide layer from the ECO-formed SiO₂ was crucial in improving electron emission characteristics. The Pt/Ti OPPS field emitter, which was annealed at 600 °C for 5 h, showed an efficiency of 3.81% at      

Ge-nanocluster formation in Ge-doped polysilicon films under oxidation and heat treatment

An experimental investigation is conducted into the formation Ge nanoclusters by heat treatment of germanosilicate-glass (Si _x Ge _y O _z ) films that are produced by oxidation of Ge-doped nanostructured polysilicon. It employs Auger and IR spectroscopy, high-resolution electron microscopy, and x-ray diffraction. The process by which Ge atoms in the films are transported toward the substrate is found to include the following stages: (1) the formation of a GeO₂ and a SiO₂ phase, (2) the reduction of GeO₂ to Ge by Si, (3) Ge-crystallite nucleation, and (4) Ge-crystallite growth. Heat treatment in humid oxygen at ≥ 800°C is found to increase Ge-nanocluster size, the point of crystallization being 500°C. It is established that heat treatment at a temperature close to the Ge melting point results in complete aggregation of the germanium into clusters, with a twofold increase in both the mean size and the number of clusters. Germanium is found to accumulate at the interface between oxidized and unoxidized polysilicon.     

Low-temperature process to increase the grain size in polysilicon films

The letter describes a novel process for increasing the grain size in polycrystalline silicon films at temperatures near 500°C. This process, once perfected, could lead to mono-crystalline or large-grain, uniformly oriented polysilicon films on amorphous surfaces.     

A new polysilicon process for a bipolar device-PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSIs. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an ECL gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 /spl mu/m/SUP 2/ gate area has been achieved. Furthermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000 /spl mu/m/SUP 2/ gate area has been successfully developed.     

Nonuniform pulse code modulation encoder using double polysilicon technology

A new scheme for an A-law PCM encoder is presented. It is based on charge redistribution in a single array of 11 binary weighted capacitors. Use is made of a double polysilicon n-MOS process which is compatible with advanced integrated filter techniques such as CCDs or active LSI filters with ratioed capacitors. No operational amplifier is needed, enabling low power dissipation and standard supply voltages (+5, -5, +12 V). It also features an improved multiple access comparator with a sensitivity better than 2 mV without charge degradation from feedthrough effects.     

Development ot ohmic contacts for GaAs devices using epitaxial Ge films

Ohmic contacts to n-type GaAs have been developed using epitaxial Ge films on GaAs alloyed with Ni overlayers by solid-state diffusion at temperatures of 450/spl deg/C-650/spl deg/C. These contacts have applications to high reliability, high temperature microwave devices. Reflection electron diffraction of the Ge layers prior to deposition of the Ni overlayers reveals the presence of high quality single-crystalline films. Even after sintering, there is very little penetration of Ge into GaAs in the absence of Ni. With the presence of a Ni overlayer, significant interdiffusion between Ge and GaAs is revealed by Auger electron spectroscopic profiles. These results, together with the current-voltage characteristics of similar contacts prepared on p-type GaAs, indicate the presence of a Ge-doped n/SUP +/ layer at the Ni/Ge-GaAs interface. Ohmic contacts using epitaxial Ge films with Ta and Mo overlayers have also been investigated.     

A vertical submicron polysilicon thin-film transistor using a lowtemperature process

This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (⩽600°C). The channel length is determined by the thickness of an SiO₂ film. As a result, submicron vertical polysilicon TFT's can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation     

A new polysilicon process for a bipolar device—PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSI's. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an emitter-coupled logic (ECL) gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 µm²gate area has been achieved. Futhermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000-µm²gate area has been successfully developed.     

The sloped-wall SWAMI—A defect-free zero bird's-beak local oxidation process for scaled VLSI technology

A new scheme for a Side WAll Masked Isolation (SWAMI) process is presented which takes all the advantages provided by LOCOS without suffering its difficulties. The new SWAMI technology incorporates a sloped silicon sidewall and a thin nitride layer around the island sidewalls such that both intrinsic nitride stress and volume expansion-induced stress are greatly reduced. A defect-free fully recessed zero bird's-beak local oxidation process can be realized by the sloped-wall SWAMI. Fabrication technology and NMOS electrical characteristics will be discussed. Two-dimensional simulation of total reduction in effective channel width for ideal vertical isolation, LOCOS, and SWAMI will also be presented. A SWAMI/CMOS circuit including 60K ROM, 2.5K SRAM, and 100 segments of display driver with 5.13 × 5.22 mm²chip size has been successfully fabricated. The results indicate that SWAMI is capable of replacing LOCOS as the isolation technology for submicrometer VLSI circuit fabrication.     

An advanced sustaining technology for plasma display panel using voltage-balancing method

A cost-effective plasma display panel (PDP) sustainer employing current injection method (CIM) for energy recovery is proposed. Using a voltage-balancing technique, driver cost can be reduced by about 20%-30% compared with that of the conventional H-bridge driver by using low-voltage switches. The energy recovery performance can be improved by the current that is built up before the energy recovery operation. This buildup current is utilized to change the polarity of the panel electrode and provides additional variable to determine pulse slopes. Experimental results show that the voltage stress of switches connected in series is identically clamped to sustain voltage during sustain operation and that light is emitted more stably by independent control of the rising and falling slopes using CIM. Therefore, the proposed sustainer is expected to be suitable for a low-cost PDP sustaining driver requiring stable discharge characteristics.     

Gigabit logic bipolar technology: advanced super self-aligned process technology

A practical bipolar logic circuit, a three-stage frequency divider, has been made with advanced super self-aligned process technology (a halfmicron bipolar technology), which has been operated at clock frequencies up to 5.5 GHz.     

A new fabrication process of field emitter arrays with submicrongate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed     

A high-performance polysilicon thin-film transistor using XeClexcimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (⩽600°C) process have field-effect mobilities of 91 cm²/V·s (electrons) and 55 cm²/V·s (holes), and ON/OFF current ratios over 10 ⁷ at V_Ds=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10     

CMOS on local SOI using SIMOX technology

CMOS on local SOI, in which n-MOS/bulk and p-MOS/SOI can be selectively implemented on the same chip, has been developed. SOI regions are formed by SIMOX technology, while bulk regions are prepared by etching of the buried SiO2. A CMOS inverter fabricated on local SOI shows good transfer characteristics.     

先进的制造工艺要与先进的设计技术相结合

半导体行业的竞争总是在加速进行,当一些中国的IC设计公司刚刚开始基于130 nm工艺的设计时,德州仪器、三星、英特尔等公司已经用45 nm工艺制造出了最新设计的芯片.制造工艺的落后就意味着成本上的劣势,在没有核心专利和应用的情况下,这种劣势使得中国IC设计公司的跟随战略也变得步履维艰.     

An advanced high-performance trench-isolated self-aligned bipolar technology

This paper describes the extension of "double-poly" self-aligned bipolar technology to include a silicon-filled trench with self-aligned cap oxide isolation, a p{^+} polysilicon defined epi-base lateral p-n-p, a p{^+} polysilicon defined self-aligned guard-ring Schottky-barrier diode, and p{^+} polysilicon resistors. Experimental circuits designed with 1.2-µm design rules have shown switching delays of as small as 73 ps for ECL circuits with FI = FO = 1. ISL circuits built with the same process on the same chip as the ECL circuits exhibit a sub-400-ps switching delay. The performance of the technology has also been demonstrated by a 5-kbit ECL SRAM with a 760-µm²Schottky-clamped multi-emitter cell and 1.0-ns access time.