A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.     

Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control

The present paper addresses a new compact low-power high-speed output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push–pull output sections of two basic complementary-type input amplifiers to realize a dual-path push–pull operation of the output stage. An auxiliary biasing network integrated in the input differential stage allows the quiescent bias conditions of the class-AB output stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed output buffer against process and mismatch variations.     

1.5 V large-driving class-AB buffer amplifier with quiescent current control

A 1.5 V large-driving class-AB buffer amplifier with quiescent current control suitable for output driver application is proposed. An experimental prototype buffer demonstrated that the circuit draws only 80 /spl mu/A static current, and exhibited the rise time of 0.4 /spl mu/s and fall time of 1 /spl mu/s under a 100 /spl Omega///150 pF load.     

A low-voltage BiMOS op amp

Describes the development of a threshold implanted BiMOS amplifier IC optimized for 2-5 V operation at a supply current of 300 /spl mu/A. A nonlinear operational transconductance amplifier (OTA) buffer having on-chip feedback provides a low-impedance rail-to-rail output, and a bulk-modulated PMOS input pair extends the common-mode range. Protective-network bootstrapping makes possible subpicoampere input-bias currents below 85/spl deg/C, and improved offset stability is achieved by the choice of threshold-level stage currents. Amplifier design is straightforward and readily applied from `micropower' to `broad-band' operating ranges. The combination of these features has produced a unique high-performance integrated circuit.     

High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit

The design of a high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time. The proposed dynamic bias method not only increases the driving capability of the class-AB output stage but also maintains a small quiescent current path.     

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

A high current drive CMOS output stage with a tunable quiescent current limiting circuit

A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-to-rail buffer. A prototype with the inclusion of auxiliary pins for biasing and current monitoring purposes has been designed using the 1-/spl mu/m double-polysilicon BCD3S process of STMicroelectronics. On a single 5-V power supply, the maximum output current is 20 mA. The amplifier, biased for a total power dissipation of 1 mW, exhibits a total harmonic distortion of -58 dB at 1 kHz with 4-V peak-to-peak on a 330-/spl Omega/ load. Correct operation of the quiescent current limiting circuit has been demonstrated for a minimum supply voltage of 2.2 V.     

A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs

The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push–pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 μm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 μW, with settling times of 0.7 and 0.68 μs for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 × 48 μm².     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

A highly linear CMOS buffer amplifier

A CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described. The buffer operates from a 5-V supply, is capable of rail-to-rail operation at both the input and output, an exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 /spl Omega/ at 20 kHz.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

A low-power high-speed class-AB buffer amplifier forflat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology     

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.     

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.     

A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier

A 0.9-V 0.5-μA, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode nMOS transistors buffer a bulk-driven pMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low-voltage translinear control circuit     

Class AB CMOS amplifiers with high efficiency

A new class AB CMOS operational-amplifier principle is presented. A transconductance amplifier based on this principle exhibits small-signal characteristics comparable to those of a conventional OTA. It has, however, a superior current efficiency and its settling time is not slew-rate limited. The new class AB principle can also be used in an output stage with a well-defined quiescent current, a rail-to-rail output swing, and a good driving capability. A two-stage amplifier with both the input and output stages based on the new principle has been realized. It features a rail-to-rail input and output common-mode range, a gain-bandwidth of 370-kHz, a settling time of less than 5 μs independent of the applied step, and a power consumption of 247 μW. It drives a resistive load of 3 kΩ in parallel with a capacitive load of 400 pF when operated on a 2.5-V/-2.5-V power supply