单片集成直流-直流转换器的效率提高方法

采用SMIC 0.13μm CMOS工艺,设计实现了开关频率达到250 MHz,单片集成的降压型电源转换器。为了提高电源转换效率,该转换器中的片上电感采用非对称性设计方法,提高了电感的品质因数。采用了高密度片上滤波电容来稳定输出电压,同时对单位电容尺寸的优化设计减小了电容的等效串联电阻以及输出电压纹波。测试结果表明,芯片输入电压为3.3 V,当输出2.5 V电压时,峰值效率达到了80%,最大输出电流达到270 mA;当输出1.8 V电压时,峰值效率达到了70%,最大输出电流达到400 mA。     

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.     

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Historically, buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve a high efficiency. Unfortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efficiency converters. To mitigate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efficiency buck converter. The dramatic decrease in the inductance value is made possible by the unique bridge timing of the stacked design that causes magnetic coupling to boost the converter's efficiency by reducing the current ripple in each inductor. The magnetic coupling is realized by stacking the two inductors on top of one another, which not only lowers the required inductance, but also reduces the chip area consumed by the two inductors. The measured conversion efficiency for the prototype circuit, implemented in a 130-nm CMOS technology, shows more than a 15% efficiency improvement over a linear converter for low output voltages rising to a peak efficiency of 77.9 % for a 0.9 V output. These efficiencies are comparable to converters implemented with higher Q inductors, validating that the proposed techniques enable high-efficiency converters to be realized with small on-chip inductors.     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

A compact 1–30 μH, 1–350 μF, 5–50 mΩ ESR compliant, 1.5% accurate 0.6 μm CMOS differential ΣΔ boost dc–dc converter

Emerging high-end portable electronics demand on-chip integration of high-performance dc–dc power supplies not only to save pin count, printed circuit board (PCB) real estate, and the cost of off-chip components but also to better regulate the point of load (PoL). In the face of a widely variable LC filter, however, integrating the frequency-compensation circuit is difficult without sacrificing stability performance, which is why integrated controller ICs only cater to relatively narrow LC ranges. While ΣΔ control addresses this LC compliance issue in buck dc–dc converters with high equivalent series resistance (ESR) output capacitors, it is not clear how it applies to ΣΔ boost converters. To that end, this paper discusses, analyzes, and experimentally evaluates a prototyped 0.6 μm CMOS differential ΣΔ boost converter. Experimental results verified the switching supply was stable across 1–30 μH, 1–350 μF, and 5–50 mΩ of inductance, capacitance, and ESR while keeping output voltage variations in response to 0.1–0.8 A load and 2.7–4.2 V line changes to less than ±1.5%, peak efficiency at 95%, and switching frequency variation to less than 27%.     

A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification

In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

An Integrated Switching DC–DC Converter With Dual-Mode Pulse-Train/PWM Control

This brief presents an integrated switching converter with a dual-mode control scheme. A pulse-train (PT) control employing a combination of four pulse control patterns is proposed to achieve optimal regulation performance under various operation scenarios. Meanwhile, a high-frequency pulsewidth modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling in steady state. The converter was fabricated with a 0.35- $muhbox{m}$ digital CMOS n-well process. The entire die area, including the on-chip pads and power devices, is 1.31 $hbox{mm}^{2}$ . Experimental results show that, in the steady state, the output voltage is well regulated at 1.5 V with $pm$12.5-mV ripples in the PWM mode. The measured maximum efficiency is 91%, and the efficiency stays above 70% within the entire 500-mW power range. In transient measurements, with a 100% load step change from 50 to 100 mA, the output voltage of the converter settles within 345 ns due to the fast response of the PT control, with a maximum voltage variation of 164 mV. The converter functions well when the input supply voltage frequently varies between 2.2 and 3.3 V, with a line regulation of 29.1 mV/V.      

采用LC滤波的大功率本安Buck开关变换器

随着矿井智能化的不断推进及安全级别的不断提高,本质安全型电气电子设备正被广泛推广使用,而其中的核心控制芯片所需的电压越来越低,所以对低压大功率本安电源的需求也就越来越大。为了提高本安Buck变换器的输出功率,采用了一种在基本本安Buck变换器的输出端附加LC滤波电路的方法,分析了采用LC滤波的大功率本安Buck变换器（LC-Buck变换器）的组成及工作原理,通过实验对比得出了本安LC-Buck变换器在同等条件下可以有效提高输出功率的结论。     

Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC–DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc–dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).     

High-accuracy current sensing circuit with current compensation technique for buck–boost converter

A novel on-chip current sensing circuit with current compensation technique suitable for buck–boost converter is presented in this article. The proposed technique can sense the full-range inductor current with high accuracy and high speed. It is mainly based on matched current mirror and does not require a large proportion of aspect ratio between the powerFET and the senseFET, thus it reduces the complexity of circuit design and the layout mismatch issue without decreasing the power efficiency. The circuit is fabricated with TSMC 0.25 µm 2P5M mixed-signal process. Simulation results show that the buck-boost converter can be operated at 200 kHz to 4 MHz switching frequency with an input voltage from 2.8 to 4.7 V. The output voltage is 3.6 V, and the maximum accuracy for both high and low side sensing current reaches 99% within the load current ranging from 200 to 600 mA.     

A planar 4.5-GHz DC-DC power converter

In this paper, we present two DC-DC converters that operate at a microwave frequency. The first converter consists of a class-E switched-mode microwave amplifier, which performs the DC-AC conversion, and two half-wave diode rectifier outputs. The class-E MESFET amplifier has a minimum power-added efficiency of 86%, corresponding drain efficiency of 95%, and 120 mW of output power at 4.5 GHz. The diode rectifier has a maximum conversion efficiency of 98% and an overall efficiency of 83%. The second converter consists of a high-efficiency class-E oscillator and a diode rectifier. The class-E oscillator has a maximum efficiency of 57% and maximum output power of 725 mW. The DC-DC converter is planar and compact, with no magnetic components, and with a maximum overall DC-DC conversion efficiency of 64% for a DC input of 3 V, and the output voltage across a 87-Ω load of 2.15 V     

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.     

A continuous conduction mode low-ripple high-efficiency charge-pump boost converter

In this paper, a new continuous conduction mode (CCM) low-ripple high-efficiency charge-pump boost converter is presented. Its components include a double voltage charge pump and a low pass LC filter. The voltage boost ratio of the positive low-ripple output voltage of the proposed converter is (1 + D) where D is the duty cycle of the control switching signal waveform. Since the energy storage inductor is connected to the power source and the load at all times, the proposed converter always operates in CCM, the transient responses are fast, and the current stress on the output capacitor is reduced and the output voltage ripple is small. In this paper, the operation principles of the CCM low-ripple high-efficiency charge-pump boost converter are described in detail. Its circuitry is designed and implemented with a TSMC 0.35 μm CMOS processes whose operation frequency is 1 MHz. The circuitry is simple and the power conversion efficiency is up to 90.95 %, and the transient response is only 7 μs.     

The Doherty Power Amplifier With On-Chip Dynamic Bias Control Circuit for Handset Application

A monolithic-microwave integrated-circuit Doherty power amplifier (PA) with an on-chip dynamic bias control circuit for cellular handset application has been designed and implemented. To improve the linearity and efficiency in the operation power ranges, the base and collector biases of the amplifiers, except the drive amplifier of the main path, are controlled according to the average output power. The base biases are controlled using the on-chip circuit and collector biases by the dc/dc chip to reduce the average dc consumption power. The power-added efficiency (PAE) is improved approximately 6% by the base dynamic bias control, and approximately 14% by the collector/base dynamic control from the class AB at Pout=16 dBm, respectively. If the dc/dc converter efficiency is 100%, the PAE could be improved approximately 17.5% from class AB, reaching to 29.2% at Pout=16 dBm. In the intermediate power level from 22 to 28 dBm, the PAE is over 34.3%. The average current consumption of the PA with the dynamic bias control is 22.5 mA in urban and 37.3 mA in suburban code-division multiple-access environments, which are reduced by 36%-46.7%, compared to the normal operation. The adjacent channel power ratio is below 47.5 dBc, and the PAE at the maximum power is approximately 43.3% in the dynamic bias operations     

一种面向单片DC/DC的低压高效片上电流检测技术

本文提出并实现了一种面向电流模式单片开关DC/DC转换器的低压高效片上电流采样电路.该电路利用功率管等效电阻电流检测技术和无需OP放大器的源极输入差分电压放大技术,使电路的应用范围可低达2.3V;-3dB带宽12MHz;在最大负载电流情况下的静态电流峰值仅19μA,比常规采用功率管镜像电流检测技术的静态电流峰值低1.5个量级左右.转换器基于0.5μm 2P3M Mixed Signal CMOS工艺设计制作.测试结果表明,电流检测电路的最大检测电流1.1A,转换器的输入最低电压2.3V,重负载转换效率高于93%.     

矩阵整流器输入与输出滤波器特性的研究

矩阵整流器是一种真正的降压型四象限AC-DC变换器,可以用在各种三相电压供电的直流电源领域。鉴于矩阵整流器采用波形高频合成原理实现输入电压-输出电压的变换和输出电流-输入电流的变换,并非纯硅变换器,输入LC滤波器与输出LC滤波器的设计至关重要,并决定着整流器系统的功能、性能和可靠性。在理论分析矩阵整流器与电流源PWM整流器具有共同变换本质的基础上,采用电路DQ转换方法,建立输入LC滤波器-矩阵整流器-输出LC滤波器系统的DC等效电路,重点分析了DC特性高低对滤波器参数设计要求,进而给出设计原则和参数选择公式,并进行实验验证。     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.