A performance optimized architecture of deblocking filter for H.264/AVC

The in-loop deblocking filter is one of the complex parts in H.264/AVC. It has such a large amount of computation that almost all the pixels in all the frames are involved in the worst case. In this paper, a fast deblocking filter architecture is proposed, and it can effectively save the operating time. In the proposed architecture, two 1-D filters are introduced so that the vertical filtering and the horizontal filtering can be performed at the same time, Only 120 cycles are needed for a macroblock. Our architecture is also a memory efficient one, and only one 4×4 pixels register, one 4×4 transpose array and one 16×32 b two-port (SRAM) are used as buffers in the filtering process. The simulation and synthesis results show that, with almost the same or even smaller area than some 1-D filter based architectures before, the proposed one can save more than 40% processing time. The architecture is suitable for real-time applications and can easily achieve the requirement of processing real-time video in 1080HD (high definition format, 1 920×1 088@30 fps) at 100 MHz.     

An efficient architecture of deblocking filter with high frame rate for H.264/AVC

In this paper, we propose an efficient hardware architecture of the deblocking filter for H.264/JVT/AVC. Earlier designs have demerit of long processing time, since the reading, writing and filtering operations have been processed in each cycles. This paper proposes a new architecture that enables filtering of vertical edge concurrent with data loading as well as filtering of horizontal edge concurrent with writing to the external memory. The experimental result shows that the necessary cycle for filtering can be reduced by 38% in comparison with the conventional method and the new architecture has advantage in power consumption.     

A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter

Exploiting specific properties of the algorithm, a high-throughput pipelined architecture is introduced to implement the H.264/AVC deblocking filter. The architecture was synthesized in 0.18 μm technology and the clock frequency and area are 400 MHz and 16.8 Kgates, respectively. Also, it is able to filter 217 and 55 Frames per second (Fps) for Full- and Ultra-HD videos, respectively. The introduced architecture outperforms similar ones in terms of frequency (1.8× up to 4×), throughput, (1.5× up to 3.8×), and Fps. Moreover, extensions to support different sample bit-depths and chroma formats are included. Also, experimental results for different FPGA families are offered.     

Low-complexity high-quality adaptive deblocking filter for H.264/AVC system

Blocking artifacts always appear on the reconstructed image, particularly in a low bit-rate video coding system. This paper presents an adaptive offset method to improve image quality for H.264 decoding. First, the histogram statistic is used to analyze the correlation between the offset and the filtering performance. The best filtering performance can mostly be found at the position of three offsets. Second, the best offset can be searched for with the minimum SAE (Summation of Absolute Error) among the three candidates. This algorithm can not only keep low computations, but it can also obtain good filtering quality. The average performance can be improved about 0.25 to 0.45 dB (decibels) higher than the original H.264 deblocking filter. The blocky effect on the decoding image can be smoothed in vision.     

Design of adaptive deblocking filter for H.264/AVC decoder SOC

In this article, a design for the adaptive deblocking filter is proposed. To understand the real-time performance, a FILTER unit that can process eight pixels beside an edge simultaneously is applied in this design to increase filtering efficiency, and local memory is used to store all temporary data generated by the FILTER to reduce access to system bus. The filter makes every 4×4 sample block pipelined through the process units and achieves an efficiency of 80% for both the FILTER unit and the bus access unit. It can fulfill filtering process for a crystallographic information file (CIF, 352×288) format picture in 95 k clock cycles. The proposed design is part of a H.264/AVC decoder system-on-chip (SOC), which is fabricated in 0.18 μm complementary metal oxide semiconductor (CMOS) process. The filter module consists of 60 k gates and 25.7 kb static random access memory (SRAM) and it can filter a macro-block in 240 clock cycles.     

Variable block-based deblocking filter for H.264/AVC on low-end and low-bit rates terminals

H.264/AVC supports variable block motion compensation, multiple reference frames, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with previous video coding standards. While these coding techniques are major functions for video compression improvement, they lead to high computational complexity at the same time. For the H.264 video coding techniques to be actually applied on low-end/low-bit rates terminals more extensively, it is essential to improve the coding efficiency. Currently the H.264 deblocking filter, which can improve the subjective quality of video, is hardly used on low-end terminals due to computational complexity.In this paper, we propose an enhanced method of deblocking filter that efficiently reduces the blocking artifacts occurring during the low-bit rates video coding. In the ‘variable block-based deblocking filter (VBDF)’ proposed in this paper, the temporal and spatial characteristics of moving pictures are extracted using the variable block-size information of motion compensation, the filter mode is classified into four different modes according to the moving-picture characteristics, and the adaptive filtering is executed in the separate modes. The proposed VBDF can reduce the blocking artifacts, prevent excessive blurring effects, and achieve about 30–40% computational speedup at about the same PSNR compared with the existing methods.     

H.264/AVC运动估计算法的硬件结构研究

运动估计是H.264/AVC编码器的重要组成部分,其运算量占据了整个编码器计算时间的60%~90%。对H.264/AVC运动估计的几种快速搜索算法进行分析比较,并在此基础上提出先进的六边形搜索算法。给出运动估计快速搜索算法的一般硬件结构,并在此基础上提出具有流水线并行处理能力的先进六边形搜索算法的硬件结构。实验结果表明：该硬件结构系统工作频率能够达到109.06 MHz,完全能够满足高清视频实时应用的要求。     

Enhanced pipelined architecture of H.264/AVC intra prediction

This paper presents a high-performance encoder for H.264/AVC intra prediction. Due to long data dependency loop of intra 4×4 prediction and complex algorithms, improving encoding speed turns into a stumbling block we have to face. To solve this problem, we first propose a pipelined method in and between macro blocks with new block processing order to accelerate the encoding speed. Benefiting from the pipelined method, reconstructed pixels of up-right blocks are available for two blocks in a macro block which could not take advantage of reconstructed pixels of up-right blocks in JM. So diagonal down left mode and vertical left mode are effective for these two blocks, which ultimately achieves a better bit-rate. Secondly, all 4×4 mode formula sharing method is proposed to reduce the redundancy of predicting formulas. Thirdly, streamlined reconstruction method is applied to improve the performance of reconstruction. CAVLC encoder with three parallel units is proposed to improve entropy coding speed significantly. As a result, it takes 268 cycles to encode a macro block. The experimental results indicate that synthesized into a 0.18 µm CMOS cell library, the new architecture only requires about 238K gates and it is able to encode 1080pHD video sequences at 30 frames per second (fps), at the operating frequency of 56 MHz.     

Mode dependent loop filter for intra prediction coding in H.264/AVC

In this paper, a high performance and low complexity loop filter is proposed for intra prediction coding. Although the deblocking loop filter (DLF) has achieved outstanding performance on suppressing quantization noise, it also induces details information loss because of the smoothing operation. To achieve better restoration performance, we propose a filter set named mode dependent loop filter (MDLF) which adaptively select the filter coefficients according to various local characteristics. In the homogeneous areas, the task of the filter emphasizes on smoothing the noise. In the heterogeneous areas, the proposed filter concentrates on preserving the details. Based on the spatial correlation assumption and statistical analysis, the intra mode combination is used to classify the training samples with different local characteristics. Then the classical least mean square error framework is employed to solve the coefficients for the proposed filter set. In this way, a more efficient adaptive loop filter scheme can be achieved for specific intra mode combination. Experiment results show that the proposed loop filter achieves superior coding gains compared to the H.264/AVC High Profile. Furthermore, relative to QALF+DLF, a comparable performance also can be achieved by the proposed MDLF with far less complexity increase.     

An Adaptive Motion Estimation Architecture for H.264/AVC

We introduce a variable block size motion estimation architecture that is adaptive to the full search (FS) and the three-step search (3SS) algorithms. Early termination, intensive data reuse, pipelined datapath with bit serial execution, and memory access management tailored to the search patterns of the FS and 3SS form key features of the architecture. The design was synthesized using Synopsys Design Compiler and 45nm standard cell library technology. The architecture sustains real-time CIF format with an operational frequency as low as 17.6MHz and consumes 1.98 mW at this clock rate. This architecture with its 500MHz peak operational frequency provides the end-user with the flexibility of choosing between video quality and throughput based on power consumption and processing speed constraints.     

高效的H.264并行编码算法

 CABAC是H.264/AVC视频压缩标准主要档次中采用的熵编码机制,结合RDO模式选择技术,可以降低20％的编码码率,但是编码器计算复杂度却同时大大增加.对算法进行并行化是有效加快编码速度的方法,但是,由于CABAC具有自适应编码的特点和RDO模式选择对熵编码的使用,使得顺序编码的宏块之间存在着严格的数据相关性,限制了并行编码算法的开发.本文结合基于宏块区域划分的数据级并行编码机制MBRP和码率估计技术,为采用CABAC熵编码机制的H.264编码算法提供了一种高效的并行编码方案:将H.264编码算法划分为模式选择和码流生成两个部分,使之构成典型的生产者-消费者关系;将RDO模式选择中的CABAC替换为码率估计,去除模式选择过程中因CABAC导致的严格数据相关性;对模式选择部分采用MBRP并行机制;码流生成部分由单独的处理器完成,并和模式选择部分实现流水化并行处理.通过4处理器系统模拟器进行实验,发现在保持视频压缩性能几乎不变的情况下,该并行算法的加速比可以达到4.7.     

基于H.264/AVC的视频信息隐藏算法

在H.264/AVC的帧内预测环节,调制H.264/AVC编码中I帧4×4亮度块的帧内预测模式实现信息隐藏.这种调制基于该模式与待隐藏比特之间的映射规则进行.宿主4×4块的具体位置由各块自身特点结合密钥所指定的嵌入位置模板确定.信息的提取过程不需要原始视频内容,也不需完全解码,而只要对码流中的帧内预测模式进行解码即可.     

FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding

Motion estimation is a highly computational demanding operation during video compression process and significantly affects the output quality of an encoded sequence. Special hardware architectures are required to achieve real-time compression performance. Many fast search block matching motion estimation (BMME) algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose three new hardware architectures of fast search block matching motion estimation algorithm using Line Diamond Parallel Search (LDPS) for H.264/AVC video coding system. These architectures use pipeline and parallel processing techniques and present minimum latency, maximum throughput and full utilization of hardware resources. The VHDL code has been tested and can work at high frequency in a Xilinx Virtex-5 FPGA circuit for the three proposed architectures.     

General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding

The latest international video-coding standard H.264/AVC significantly achieves better coding performance compared to prior video coding standards such as MPEG-2 and H.263, which have been widely used in today’s digital video applications. To provide the interoperability between different coding standards, this paper proposes an efficient architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC intra frame transcoding, using the original information such as discrete cosine transform (DCT) coefficients and coded mode type. Low-frequency components of DCT coefficients and a novel rate distortion cost function are used to select a set of candidate modes for rate distortion optimization (RDO) decision. For H.263 and H.264/AVC, a mode refinement scheme is utilized to eliminate unlikely modes before RDO mode decision, based on coded mode information. The experimental results, conducted on JM12.2 with fast C8MB mode decision, reveal that average 58%, 59% and 60% of computation (re-encoding) time can be saved for MPEG-2, H.263, H.264/AVC to H.264/AVC intra frame transcodings respectively, while preserving good coding performance when compared with complex cascaded pixel domain transcoding (CCPDT); or average 88% (a speed up factor of 8) when compared with CCPDT without considering fast C8MB. The proposed algorithm for H.264/AVC homogeneous transcoding is also compared to the simple cascaded pixel domain transcoding (with original mode reuse). The results of this comparison indicate that the proposed algorithm significantly outperforms the mode reuse algorithm in coding performance, with only slightly higher computation.     

Error concealment via Kalman filter for heavily corrupted videos in H.264/AVC

Error concealment at the decoder side is an economical approach to ensuring an acceptable and stable video quality in case of packet erasure or loss, and thus it has attracted lots of research interest. Current techniques mainly employ the spatial or temporal correlation to predict the motion vectors (MVs) of the missing blocks, and interpolation, extrapolation or boundary matching schemes are usually effective. However, for heavily corrupted sequences, e.g., with macroblock loss rate beyond 50%, most methods might perform less satisfactorily. Inspired by the tracking efficiency of Kalman filter (KF), in the present work, we adopted it to predict the missing MVs, and the unpredicted ones (minority) were recovered complementarily using the bilinear motion field interpolation (MFI) method. Since the KF prediction is independent of the loss rate, the present framework is especially robust for heavily corrupted videos. Experimental results on typical sequences reveal that the proposed algorithm outperforms the boundary matching algorithm embedded in the H.264/AVC reference code, the MFI algorithm in the literature, and some other existing techniques by up to about 5.68 dB.     

一种基于H.264/AVC的高效块匹配搜索算法

本文针对H.264/AVC的编码特点,提出了一种利用时空域运动相关性的快速块匹配搜索算法.该算法充分利用了视频序列的运动程度与宏块编码模式间的关联特性以及运动矢量的统计特征,明显减少了运动估计的搜索复杂度.实验表明,本文方法的搜索速度分别比FS和DS算法平均提高了77.96%和32.19%;重建图像的PSNR比DS算法平均提高了0.06dB,更接近FS算法的编码质量.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

H.264/AVC video for wireless transmission

H.264/AVC will be an essential component in emerging wireless video applications thanks to its excellent compression efficiency and network-friendly design. However, a video coding standard itself is only one component within the application and transmission environment. Its effectiveness strongly depends on the selection of appropriate modes and parameters at the encoder, at the decoder, as well as in the network. In this paper we introduce the features of the H.264/AVC coding standard that make it suitable for wireless video applications, including features for error resilience, bit rate adaptation, integration into packet networks, interoperability, and buffering considerations. Modern wireless networks provide many different means to adapt quality of service, such as forward error correction methods on different layers and end-to-end or link layer retransmission protocols. The applicability of all these encoding and network features depends on application constraints, such as the maximum tolerable delay, the possibility of online encoding, and the availability of feedback and cross-layer information. We discuss the use of different coding and transport related features for different applications, namely video telephony, video conferencing, video streaming, download-and-play, and video broadcasting. Guidelines for the selection of appropriate video coding tools, video encoder and decoder settings, as well as transport and network parameters are provided and justified. References to relevant research publications and standardization contributions are given.     

一种改进比特分配的H．264／AVC码率控制算法

提出了一种新的改进的H．264／AVC码率控制算法,克服了MAD不能客观、准确的反映出整个图像的复杂度的问题,引入了一个新的MADMV参数,使包括纹理比特和头比特的图像复杂度得到准确的预测。实验结果表明,与JVT-G012相比,该方法可以在准确控制码率的同时,图像的视觉质量也有相应的提高。     

一种改进的H.264/AVC帧层码率控制算法

针对JVT-G012算法在帧层对P帧目标比特分配太过均匀,忽略了图像复杂度的问题,提出了一种简单有效的帧差比值法来进行帧层目标比特的分配,并利用缓冲区充盈度来调整当前帧量化参数的方法.通过大量实验仿真表明,与JVT-G012算法相比,该算法不仅能够更精确地控制码率,而且还提高了视频图像的质量.