Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced ΔV_T can be reduced to a quarter of ΔV_T found after the static NBT stress.     

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

The effects of intermittent low-bias annealing on NBT stress-induced threshold voltage shifts in p-channel VDMOSFETs are analysed in terms of mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Negative bias annealing after an initial NBT stress appears to freeze the initial degradation. Alternatively, either positive or zero bias removes the portion of stress-generated oxide-trapped charge and creates new reversible component of interface traps, while each repeated NBT stress regenerates the oxide-trapped charge and removes the reversible component of interface traps. The post-stress generation of interface traps under positive oxide field is ascribed to the processes at SiO₂/Si interface arising from the reversed drift direction of positively charged species, which are not likely to occur under negative gate bias. Despite all these phenomena, intermittent annealing does not seem to affect the device lifetime.     

Measurement considerations for evaluating BTI effects in SiC MOSFETs

In this paper, we review the phenomenon of bias-temperature instability (BTI) in SiC MOS devices, with an emphasis on the effects of metrology. The complex behavior of the charge trapping mechanism responsible for V_T instability requires careful consideration of measurement conditions and precise control of the associated parameters to produce meaningful results. Preconditioning the devices to be tested, as well as making faster measurements, will elicit the truest response. Any bias interruption or delay between stressing and measurement will produce a large deterioration in the original V_T drift caused by the stressing, though this can be effectively counteracted by briefly reapplying the stress bias before measurement.     

On the importance of the Vg,max-Vth parameter on LTPS TFT stressing behavior

In this work we point out the importance of the device parameter V_g,max-V_th (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (V_th, G_m,max, S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar G_m,max degradation, as well as similar V_g,max-V_th evolution. Therefore, G_m,max evolution with stress time was found to be related more strongly to tail state generation, probed through V_g,max-V_th, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant G_m,max reduction could only be probed through the observation of V_g,max-V_th, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense G_m,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by V_g,max-V_th evolution with stress.     

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T_phy) hafnium oxide (HfO₂)/silicon dioxide (SiO₂) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

Study of nitrogen impact on VFB-EOT roll-off by varying interfacial SiO2 thickness

Flat band voltage (V_FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO₂/nitrided-HfSiO stacks. V_FB increases when SiO₂ interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO₂ interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO₂ interface through the SiO₂ layer in thinner SiO₂ device, and accumulates near Si/SiO₂ interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO₂ devices due to the higher interfacial trap density.The V_FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide.     

NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs

Negative bias temperature instability (NBTI) and hot-carrier induced device degradation in accumulation-mode Pi-gate pMOSFETs have been studied for different fin widths ranging from 20 to 40 nm. The NBTI induced device degradation is more significant in narrow devices. This result can be explained by enhanced diffusion of hydrogen at the corners in multiple-gate devices. Due to larger impact ionization, hot-carrier induced device degradation is more significant in wider devices. Finally, hot-carrier induced device degradation rate is highest under stress conditions where V_GS = V_TH.     

An input-free V extractor circuit using a series connection of three transistors

This paper describes a self-biased MOS transistor circuit with the ground referenced output voltage equal to the threshold voltage V _T. The circuit employs a series connection of three transistors where the middle transistor is in linear operation and external transistors are in saturation. The circuit can be applied for V _T extraction of both n-channel and p-channel transistors. The range of currents for better measuring of V _T in each case is established by simulation.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs have been investigated to get better insight into the NBTI phenomena. Negative bias annealing does not affect stress-induced degradation significantly, whereas either zero or positive bias annealing removes the portion of stress-induced oxide-trapped charge while creating additional interface traps. The removable component of stress-induced oxide-trapped charge is found to decrease, and influence of external bias on annealing phenomena weakens with duration of preceding stressing, suggesting that extended stress moves the trapped charge to energetically deeper oxide traps, which are more difficult to anneal.     

Threshold voltage degradation in plasma-damaged CMOS transistors — Role of electron and hole traps related to charging damage

The paper presents results of study of threshold voltage (V_T) degradation in CMOS transistors damaged by high-field charging. Fowler-Nordheim stress induced V_T degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. “Direct” and “reverse” antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously.     

Trapping,emission and generation in MNOS memory devices

This study is concerned with trapping phenomena occuring at the semiconductor-oxide interface and in the nitride layer of variable-threshold metal-nitride-oxide-semiconductor (MNOS) memory devices. The technique consits of biasing the device in such a manner as to charge or discharge either the interface traps or the nitride traps, or both sets of traps simultaneously. The device is then cooled to low temperature with the bias still applied, and at the low temperature the biasing condition is changed, in order to induce the device into a non-steady mode that is quasi-stable at the low temperature. The temperature of the device is then raised at a constant rate, and the resulting current vs temperature (I-T) characteristics is found to be rich in structure. By means of a series of systematic experiments the various portions of the I-T characteristic are identified with emission of electrons from interface states and the nitride traps, and surface generation. From this data the energy distribution of interface states is determied. It is shown that the memory charge in the nitride is distributed throughout the nitride, and temporary memory charge and semi-permanent memory charge are distinguished.     

Influence of fin number on hot-carrier injection stress induced degradation in bulk FinFETs

In this paper, hot-carrier injection (HCI) stress has been used to investigate the reliability of n-channel FinFET devices with different fin numbers. Threshold voltage (V_TH) shift, subthreshold swing and transconductance variation were extracted to evaluate the degradation of the device under stress. FinFET devices with fewer fins show more serious performance degradation due to hot-carrier injection stress. It is suggested that the existing of coupling effect between neighboring fins reduces the inversion charge density and equivalent electric field in multi-fin devices, which causes better reliability than single-fin devices.     

NBTI related degradation and lifetime estimation in p-channel power VDMOSFETs under the static and pulsed NBT stress conditions

The effects of static and pulsed NBT stressing on threshold voltage in p-channel power VDMOSFETs are analysed, and the results are compared in terms of the effects on device lifetime. The results obtained by both “1/V_G” and “1/T” models, which are used for extrapolation to normal operation voltages and temperatures, respectively, indicate the device lifetime could be much longer under the pulsed stress conditions than under the static ones. It is also shown that lifetime tends to increase with decreasing the duty cycle of pulsed stress voltage applied.     

Numerical modeling of looped C-V Characteristics in Ap+n junction containing mid-bandgap electron traps

The capacitance of p⁺n junctions containing traps or deep centers depends on the time variation of the applied reverse voltage. Capacitance changes results from the time dependent variation of the density of traps filled with electrons within the depletion region. If a cyclical reverse voltage in applied to the junction, capacitance hysteresis due to the time-dependent charge variation within the depletion region should be observed. The hysteresis loops, as a function of the bias drive rate, temperature, and total concentration of traps provide some information on the characteristics of the traps.This paper presents a numerical analysis of looped C-V characteristics in a p⁺n junction containing midbandgap electron traps and also discusses the variation of loops as a function of the bias drive rate, dV/dt, total concentration of traps, N_T, and emission rates of electrons and holes, e_n and e_p, based on our numerical modeling.     

Effect of hydrogen annealing on hot-carrier instability of X-Ray irradiated CMOS devices

In the very large scale integration (VLSI) technology, the need for high density and high performance integrated circuit (IC) chip demands advanced processing techniques that often result in the generation of high energy particles and photons. Frequently, the radiation damage are introduced by these energetic particles and photons during device processing. The radiation damage created by x-ray irradiation, which can often occur during metal sputtering process, has been shown to potentially enhance hot-carrier instability if the neutral traps which act as electron or hole traps in the silicon dioxide is not annealed out. In this paper, we investigate the effects of annealing using different hydrogen contents and temperatures on the device characteristics and hot carrier instability of 0.5 μm CMOS devices after 1500 mJ/cm² synchrotron x-ray irradiation. Three different annealing conditions were employed; 400° C H₂, 450° C H₂, and 400° C H₂ + N₂. It is found that for all three different hydrogen anneals the normal characteristics of irradiated CMOS devices can be effectively recovered. The hot-carrier instability of bothp- andn-channel MOSFETs are significantly enhanced after x-ray irradiation due to the creation of neutral traps and positively charged oxide traps. After high H₂ (100%) concentration anneals at 450° C, the hot-carrier instability in irradiatedn-channel devices is greatly reduced and comparable to the non-irradiated devices. Although the hot-carrier instability inp-channel devices is also significantly reduced after annealing, the threshold voltage shifts are still enhanced as compared to the devices without exposure to x-ray irradiation during maximum gate current stress. For those non-irradiated, but hydrogen-annealedp-channel devices, the hot-carrier instability was observed to be worse than the non-irradiated device without hydrogen annealing.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Germanium surface and interfaces (Invited Paper)

Germanium surface and interfaces are modeled based on the requirement that surface charge neutrality is satisfied. It is found that Ge interfaces have remarkable electronic properties stemming from the fact that the energy gap is low and the CNL is located very low in the gap close to the valence band. Because of this, acceptor defects (probably dangling bonds) are easily filled building a negative charge at the interface which easily inverts the surface of n-type Ge at no gate bias and for low doping N_D and moderate to high interface state density D_it. This has important consequence in the electrical characteristics of Ge transistors. In p-channel FETs, an undesired positive threshold voltage V_T of +0.2 to +0.5 V is predicted depending on N_D, D_it and the equivalent oxide thickness. In n-channel FETs, inversion is inhibited and V_T could become higher than 1 V if the D_it is well in excess of 10¹³ eV^?1 cm^?2.     

Punch-through currents in P+NP+ and N+PN+ sandwich structures—II: General low-injection theory and measurements

Analytical one-dimensional exponential expressions are derived for the current/voltage characteristics of the punch-through effect in devices where a certain bias voltage is needed to bring the device into punch-through (V_PT > 0) and where punch-through is already present in the non-biased condition (V_PT = 0). Measurements show that the theory can describe the current/voltage relations adequately at low current levels.