Early integration of safety to the mechatronic system design process by the functional failure identification and propagation framework

The research goal of this paper is to introduce a risk analysis methodology that can be applied at the early concept design phase, whose purpose is to identify fault propagation paths that cross disciplinary boundaries, and determine the combined impact of several faults in software-based automation subsystems, electric subsystems and mechanical subsystems. Specifically, the Functional Failure Identification and Propagation (FFIP) analysis framework is proposed to perform a simulation-based analysis of functional failure propagation. The focus is on risk assessment, the earliest activities of the safety process, in which hazards are identified and safety requirements are derived. It is argued that current risk assessment methods are not sufficient for concurrent integration of the safety process to the design process of a complex mechatronic system. In order to facilitate the integration of risk assessment to such systems at the earliest design stages, the design is expressed with syntax and semantics that is able to describe the propagation of failures throughout the system and especially across the boundaries of the mechatronic domains. A boiling water nuclear reactor (limited to the reactor core and steam outlets) is used as a case study. The results demonstrate the capability to handle several fault propagation paths in one scenario for hazard identification at the early, functional, design stage. Specifically, it is shown that FFIP is able to identify fault propagation paths that cross disciplinary boundaries, and which in turn is able to determine the combined impact of several faults in software-based automation subsystems, electric subsystems and mechanical subsystems. The impact is expressed in degradation or loss of safety related functions.     

Fault isolation in semiconductor product,process, physical and package failure analysis: Importance and overview

Failure analysis plays a major role in all areas of the semiconductor company especially during product development cycle, 1st silicon stage, or in wafer processes and fabrication as well as assembly and package development. Different companies have different FA flows but all FA steps will need to start with fault isolation. Fault isolation is the step to narrow down the focus area of a failing component or product to a manageable area that will allow us to (a) improve success of finding the defect that is causing the failure and, (b) significant speed up turn-around time for analysis.This paper provides an overview of all the available failure analysis on fault isolation methodologies and tools, for device/product level and expanding to package/assembly and PFA level isolation. The aim of the paper is to provide sufficient depth to each topic including some case studies to emphasize the key points related to each methodology. The tutorial will also cover some future directions/roadmaps.     

信息系统集成过程中存在的风险问题研究

随着计算机技术、网络技术以及通信技术的飞速发展,我国现代化企业的信息化水平得到了快速的提升。其中办公自动化、管理信息系统等多种信息系统对其企业以及其政府部门的工作都起到了前所未有的推动作用。在企业的发展当中,随着规模的不断扩大,也需要对企业内部的信息系统作出有效的共享,不断地加强企业内部的各部门之间的信息交流。在文章当中首先对信息系统集成进行了概述;其次对信息系统在集成当中存在的问题作出了分析;最后在实际应用的基础上提出了改善的措施。     

基于ZigBee技术的快件寻找系统设计

针对快件派送环节,快递员从数量繁多的快件中难以寻找目标快件的问题,设计基于ZigBee技术的快件寻找系统,通过采用网状网络拓扑结构,构建包含快件终端节点、快递员节点、手机APP监控中心3个层次的系统架构,重点设计快件终端节点和快递员节点的CC2530无线通信模块和软件流程,并提出时间同步协议算法,实现全网节点的同步休眠和唤醒,降低整个系统的功耗,延长系统的工作时间。实验测试结果表明,系统能够准确地寻找目标快件,减少派送时间,实现设计效果。     

基于集成技术的智能化信息系统设计

为解决中小物流企业在区域物流信息系统应用中存在的问题,以上海市生活垃圾内河集装化转运系统为例,根据系统运营背景和智能化建设目标,设计了四层架构的系统原型并给出了具体部署方案.在此基础上,研究系统关键技术的集成路线,分析其在系统架构各组件中的应用,从而实现了生产作业管理、船舶靠泊调度、资产管理、数据统计报表管理、作业监控指挥中心等子系统的功能,提高了系统智能信息化管理能力.     

Accelerated life test of high power white light emitting diodes based on package failure mechanisms

Accelerated life tests of high-power white light emitting diodes (LEDs) were conducted under an unbiased highly accelerated temperature and humidity test (HAST) and a normal aging test. The conditions in the unbiased HAST were 110 °C-85% RH, 130 °C-85% RH without bias. During the aging, the degradation mechanisms of optical power reduction and degradation of 455 mm blue wavelengths that were better than phosphors related yellow emission bands were observed. The microscopy analysis showed that this effect could be ascribed to the bubbling and discoloration of the silicone encapsulating material of the package. It is thought that these features are also responsible for the optical power reduction and thermal resistance increase.     

等离子清洗在LED封装工艺中的应用

在LED封装工艺过程中,器件表面的氧化物及颗粒污染物会降低产品可靠性,影响产品质量。如在封装前进行等离子清洗,则可有效去除上述污染物。介绍了等离子清洗设备原理,并对清洗前后的效果做了对比。     

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this first wafer level package of CMOS Image Sensor (CIS), the integration on the z axe will continue by the wafer lens integration for a continuous form factor and low cost module.First 3Di applications with TSV is entering the market with the via-last approach, more simply to be developed in semiconductor manufacturing in order to secure the 3Di technologies and to promote the 3Di to customers. Then specific design and electrical models will be developed and optimized allowing a fast and prosperous development of the via-first approach.A challenge in the modelisation of the TSV is the understanding of the mechanical impact of the trench and the metal filling on the behavior of the CMOS components and the reliability. These types of researches are progressing in various institutes and are essential for an increasing integration of TSV.Because actually, the technology continues to drive the 3D roadmap, the mechanical and thermal modelisation and 3D design tool need to be more activated to be developed faster in order to optimize the 3D module. Then the electrical testing will be a real challenge to be able to distinguish drift in the right strata, to be able to isolate a via within more than 10000 via in a module. The electrical testing will be strictly linked to mechanical and electrical failure analysis to get feed-back in technology, actual drawback of the 3D development.The cost of the 3Di and the TSV integration is more and more important and looks as a primary driver even if the functionalities increase faster than cost! Some steps have been already identified to be more costly steps: bonding and via filling. Indeed, throughput and material used have a direct impact on the final price.Continuous perspectives of TSV integration are progressing in order to optimise actual applications or to develop new integration. First challenging integration is the interposers with 3D interconnection allowing devices mounting on both side, like passive device integration or building of micro-cooling channels. The main interest of the 3D silicon interposer is the fact that it can connect chips at different locations and sizes, as example memory over digital IC. The usage of silicon as an interposer leads to an increase in the cost, but it will boost performances and reduce power consumption. One other advantage of the introduction of 3D interposer is the simplification of the required substrate implying a better mismatch of CTE lowering the packaging failure.In the wafer level package, TSV is now introduced to reduce the package footprint and mainly simplify the capping of device, similar to that for the MEMS. Indeed by integrating TSV, the capping must only protect the device against external environment, and not also take into account the electrical path in the bond layer degrading the hermiticity performance.To finish this paper, the sentence of Yann Guillou is the right situation: “The (3D) roadmaps need to be based on application requirements and not driven by technology ONLY. 3D Integration with TSV is not a scaling based concept Does it make sense today to think about submicron via diameter or dice thinner than 30 μm for example?” Applications need to take a risk by using 3D TSV technology!     

基于虚拟化技术的服务器端数据整合系统设计研究

为实现服务器端数据最大限度整合,提升数据利用率,保障数据安全性,设计基于虚拟化技术的服务器端数据整合系统。系统总体框架以虚拟机和物理节点作为系统管理对象,通过服务器端进行数据整合,执行客户端命令并监测物理节点状态,采用网络监控软件采集,整合服务器端数据。依据该结果明确选择单独服务器还是虚拟服务器,并制定服务器端数据整合方案。实验结果表明,该系统功能实用性较强,稳定性高,并且系统在进行数据整合时所需时间少,可以实现高效率运行。     

基于SOA的工作流系统集成研究与设计

SOA的软件架构也能为企业未来的下一步信息化建设提供更便捷的服务,更易于软件的移植或重用。在此为了开发出符合业务流程的工作流系统,以管理企业的业务需求为出发点,通过研究与分析工作流系统集成的关键技术,采用SOA的思想,把一些方法封装为服务,将其开发为基于SOA的工作流系统。这在最大程度上解决企业现有应用信息系统间的耦合,也便于后续开发的系统与现有系统保持一致的规范。     

基于层次分析法的中文分词算法改进

首先简要介绍了中文分词的应用领域,指出中文分词所面临的问题,歧义语句和未登录词的识别率低的现状。然后,在传统的机械分词算法基础上,改进算法,引入了多种优化技术。基于上述理论和改进算法,设计并实现了一个改进的中文分词系统,不仅能够保证快速分词,而且提高了分词的正确率,改善了歧义语句和未登录词的识别率低的问题。     

基于DSP的信号处理系统的设计

根据井下信息处理的需要,本文设计了一种基于TMS320F2812的信号处理系统。采用具有AD模数转换功能的32位DSP芯片TMS320F2812实现井下信息的实时采集处理,将处理后的数据通过SCI（串行异步通信接口）传送到PC,由PC的串口调试工具对接收信号进行实时显示和具体分析并将结果反馈给DSP进行控制。本文对硬件和软件设计进行了详细描述,该系统具有很高的可靠性和通用性,具有高速数据采集功能。12位的精度完全满足现场对数据精度的要求。     

Use of C-SAM acoustical microscopy in package evaluations and failure analysis

Acoustical microscopy is gaining wide acceptance in the microelectronic packaging community. C-mode scanning acoustical microscopy, C-SAM, is widely used in package evaluations and for failure analysis. This paper discusses several specific topics. These include: (1) popcorn cracking in SMDs; (2) an evaluation of solder die attach in power packages; (3) an instance of top of die delamination which resulted in electrical failures; and (4) moisture sensitivity of other surface mount power packages and how it resulted in ball bond degradation during a new product qualification.     

基于调频广播的单站无源定位系统的威力估计

基于调频广播的单站无源定位系统实际相当于收发分置的双基雷达,其直达波和地杂波的传播为小擦地角的低空传播,且影响威力范围的因素随基线长度的变化而有所不同.本文考虑低空传播,分析了不同基线长度时影响观测范围的主要因素,推导了对应情况下对高空飞行目标的观测面积的计算公式.结合上述公式以及对参考天线的要求可以得到最优的基线距离.仿真实验验证了上述的分析,并指出降低收发天线的高度可以进一步提高观测面积.     

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.     

基于机器视觉的香烟小包装外观质量检测系统

讨论了基于机器视觉的香烟小包装外观质量在线检测系统总体方案的设计,并针对香烟小包装流水线的具体情况,分别对香烟小包的检测位置以及图像采集方案进行了探讨。文中采用了一种用于香烟包装质量检测的快速图像匹配算法,并利用开源计算机视觉库OpenCV进行算法实现,仿真实验结果表明,该图像匹配算法计算速度快、检测精度高,满足香烟包装质量检测的需要。     

基于机器视觉的香烟小包装外观质量检测系统

讨论了基于机器视觉的香烟小包装外观质量在线检测系统总体方案的设计,并针对香烟小包装流水线的具体情况,分别对香烟小包的检测位置以及图像采集方案进行了探讨.文中采用了一种用于香烟包装质量检测的快速图像匹配算法,并利用开源计算机视觉库OpenCV进行算法实现,仿真实验结果表明,该图像匹配算法计算速度快、检测精度高,满足香烟包装质量检测的需要.     

基于FPGA的直流电动机伺服系统改进

随着电子技术的发展,直流电机控制的方式正在发生着很大的变化。当计算机进入控制领域后,PWM脉宽调制方式已经成为电机控制的主流。随着可编程逻辑器件的出现,又给直流电机的伺服提供了新的方法和手段。文中系统利用FPGA作为主控制芯片,利用VHDL语言在片内实现分频模块,AD控制模块,反馈控制模块等,最后完成对PWM波形的脉宽调制,从而达到对电机的转速、正转或者反转等等参数的控制。在Quartus II软件上仿真后说明采用位置反馈、速度反馈和电流反馈对直流电机进行控制更精确,更可靠。     

基于多网融合的电力应急通信系统设计

各类突发事件和自然灾害给电力设施的正常运行造成严重威胁,因此,迫切需要建立高效、稳定的电力应急通信系统。基于单一的网络载体的通信系统难以满足复杂多变的应用环境。文中采用多网融合技术,实现卫星通信、4G、Wi-Fi等多个子网络载体融合的电力应急通信系统,克服单一网络的局限性,提高电力应急通信的效率。经测试验证,该系统可以提高传输线路的带宽、自动切换至信号最优的网络,保障了数据传输的安全性和稳定性。