A dynamic synchronization method to realize soft defect localization applied on digital and mixed-mode analog ICs in failure analysis

Failure analysis on advanced logic and mixed-mode analog ICs more and more has to deal with so called ‘soft defects’. In this paper, a dynamic synchronization method is proposed to perform soft defect localization (SDL) technique by Optical Beam Induced Resistance Change (OBIRCH). It is a new and low-cost way to achieve SDL technique by OBIRCH equipment if there is no normal SDL equipment on hand. It extends the application of OBIRCH equipment to a more advanced failure analysis realm. The methodology and system configuration are presented. The experimental results show this dynamic synchronization method is accurate enough to locate a soft defect. Two real cases are studied on a digital IC and a mixed-mode analog IC respectively using this method.     

Investigation on marginal failure characteristics and related defects analysed by soft defect localization

Soft defect localization is a well established failure analysis technique for detecting defects causing integrated circuits to marginal fail. First simulations on Shmoo characteristics using a defect model on simple inverter logic have already been presented. However, the influence of a defect on the Shmoo characteristic for more complex circuit structures is not investigated.This paper discuss a correlation of Shmoo results to both, the defect type and failing circuit structure of a SRAM-cell. Soft defect localization has been applied on two examples showing a bridging defect with a SRAM-cell. In both cases the Shmoo characteristics show a strong voltage dependency. The effect of various bridging defects within a SRAM-cell has been simulated and discussed. With these results the Shmoo characteristic should be considered in the analysis for a defect based on soft defect localization.     

Failure analysis defect location on a real case 55 nm memory using dynamic power supply emulation

Static and dynamic techniques for defect location are well established in the failure analysis flow of a failing integrated circuit. When a circuit shows an overconsumption on power supply, the useful static techniques are laser stimulation (OBIRCH, TIVA, LIVA, etc.) or photoemission. When the electrical signature is a soft fail, a functional fault or a timing issue the analyst will use dynamic techniques like dynamic laser mapping (SDL, xVM, LVI, etc.), dynamic photoemission or internal probing (Ebeam, TRE, LVP, etc.) by applying a looping test sequence which emulates the fail.In this paper we will present a real case analysis on a circuit showing a static signature (over consumption) and also a functional fault. Both static and dynamic location techniques have been used for the defect location, plus a non conventional approach by applying a clocked power supply sequence to the circuit. A comparison is done between the different signatures and we show that dynamic power supply emulation can bring some additional information on the defect location which is not detected with the conventional static/dynamic approach.     

Effect of physical defect on shmoos in CMOS DSM technologies

Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.     

Investigation on BIST assisted failure analysis on digital integrated circuits

Built in self tests (BISTs) on integrated circuits are one approach of maintaining fault coverage and device’s testability without increasing the test time. As an additional benefit, for the purpose of failure analysis fault simulation down to node level can be achieved. However, regarding defect localization common FA techniques are still mandatory.In this paper, we present BIST assisted case studies on functional failing integrated circuits. Starting from a fault simulation, defect localization will be done by using conventional failure analysis techniques. After successfully determining the physical defect, we will compare its effect on the affected nodes to the initial fault simulation.     

Defect Simulation Methodology for iDDT Testing

The International Technology Roadmap for Semiconductors (ITRS) identifies two main challenges associated with the testing of manufactured ICs. First, the increase in complexity of semiconductor manufacturing process, physical properties of new materials, and the constraints imposed by resolution of lithography techniques etc., give rise to more complex failure mechanisms and hard-to-model defects that can no longer be abstracted using traditional fault models. Majority of defects, in today's technology, include resistive bridging and open defects with diverse electrical characteristics. Consequently, conventional fault models, and tools based on these models are becoming inadequate in addressing defects resulting from new failure mechanisms. Second, the defect detection resolution of main-stream I_DDQ testing is challenged by significant elevation in off-state quiescent current and process variability in newer technologies. Overcoming these challenges demands innovative test solutions that are based on realistic fault models capable of targeting real defects and thus, providing high defect coverage. In prior works power supply transient current or i_DDT testing has been shown to detect resistive bridging and open defects. The ability of transient currents to detect resistive opens and their insensitivity (virtually) to increase in static leakage current make i_DDT testing all the more attractive. However, in order to integrate i_DDT based methods into production test flows, it is necessary to develop a fault simulation strategy to assess the defect detection capability of test patterns and facilitate the ATPG process. The analog nature of the test observable, i.e., i_DDT signals, entail compute intensive transient simulations that are prohibitive. In this work, we propose a practical fault simulation model that partitions the task of simulating the DUT (device under test) into linear and non-linear components, comprising of power/ground-grid and core-logic, respectively. Using divide-and-conquer strategy, this model replaces the transient simulations of power/ground-grid with simple convolution operations utilizing its impulse response characteristics. We propose a path isolation strategy for core-logic as a means of reducing the computational complexity involved in deriving i_DDT signals in the non-linear portion. The methodology based on impulse response functions and isolated path simulation, can enable i_DDT fault simulation without having to simulate the entire DUT. To our knowledge, no practical technique exists to perform fault simulation for i_DDT based methods. The proposed fault simulation model offers two main advantages, first, it allows fault induction at geometric or layout level, thus providing a realistic representation of physical defects, and second, the current/voltage profile of power/ground-grid, derived for i_DDT fault simulation, can be used to perform accurate timing verification of logic circuit, thus facilitating design verification. In summary, the proposed fault simulation framework not only enables the assessment of defect detection capabilities of i_DDT test methodologies, but also establishes a platform for performing defect-based testing on practical designs.     

Improved SRAM failure diagnosis for process monitoring via current signature analysis

SRAM's are frequently used as monitor circuits for defect related yield, due to the ease of testing and the good correlation to the yield characteristics of logic circuitry. For the identification of the failure/fault type and the nature of the defect causing the failure, measured failbitmaps are mapped onto a failbitmap catalog obtained from defect-fault simulation. Often this mapping is not unique. A given failbitmap can be caused by several faults or defects.In this contribution, the application of current signature analysis is demonstrated for a stand-alone 16kx1 SRAM monitor circuit. It is found that the resolution of the failbitmap-fault-defect catalog can be improved considerably by additional current signature measurements. The interpretation of current measurements is based on simulation of the possible faults contained in the failbitmap catalog under the operating conditions in the current test. There was good agreement between the simulated and measured current values.With the aid of current measurements, more yield learning information is obtained from the process monitoring vehicle. In some cases, the shorted nodes inside a SRAM cell can be determined exactly. This eases the localization of the failure and is of practical importance for the sample preparation in physical failure analysis.     

An adaptive simulation framework for AMS-RF test quality

Ensuring the quality of a circuit implies ensuring the quality of test. Despite the fact that performance-based testing has been the golden standard for Analog, Mixed-Signal and RF test for decades, high-reliability markets like automotive have found that functional test leaves some potential defects undetected that can produce in-field failure. There is thus a push towards defect-oriented testing which, in turn, calls for an efficient defect simulation framework. This paper presents a statistical adaptive defect simulation based on likelihood-weighted random sampling to evaluate the quality of AMS-RF tests in terms of defect coverage and fault escape. The adaptive loop takes a decision at each new defect simulation on whether it is more efficient to assess the defect coverage or the fault escape rate of the test under evaluation, as a function of the desired targets for these two metrics. Several decision criteria are proposed and validated by simulation of a complete IC for different tests.     

ATPG scan logic failure analysis: a case study of logic ICs – fault isolation, defect mechanism identification and yield improvement

Yield analysis of sub-micro devices has become an ever-increasing challenge. Scan based design is a powerful concept on complex designs that is routinely employed for fault isolation. To minimize the list of defect candidates according to fault diagnosis, precise failure localization with the help of failure analysis tool is needed as a complement. This example comes from a 0.13-um technology with six layers of copper interconnect. The chip has 18 scan chains with up to 2800 flip flops in each chain. Low Automatic Test Pattern Generation (ATPG) scan chain yield was reported during final scan test. This work presents the case study illustrating the application of scan diagnosis flow as an effective means to achieve yield enhancement.     

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally.     

Modeling and testing for stuck faults in pseudo nMOS combinational circuits

In this paper, a new transistor model is developed. This model employs the logic transistor function (LTF) to examine the behavior of pseudo nMOS logic circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M). I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults are analyzed in the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specified sub circuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used.     

一种静态随机存储器型现场可编程门阵列的单粒子软错误率的软件分析方法

静态随机存取存储器(SRAM)型现场可编程门阵列(FPGA)在当前空间电子设备中取得了广泛的应用,尽管它对空间辐射引起的单粒子翻转效应极其敏感。在FPGA的配置存储器中发生的单粒子翻转造成的失效机理不同于传统的存储器中的单粒子翻转。因此,如何评价这些单粒子翻转对系统造成的影响就成了一个值得研究的问题。传统的方法主要分为辐照实验和故障注入两种技术途径。本文中提出了一种新的方法,可以用来分析单粒子翻转对构建在FPGA上的系统造成的影响。这种方法基于对FPGA底层结构以及单粒子翻转带来的失效机理的深入理解,从布局布线之后的网表文件出发,寻找所有可能破坏电路结构的关键逻辑节点和路径。然后通过查询可配置资源与相应的配置数据之间关系来确定所有敏感的配置位。我们用加速器辐照实验和传统的故障注入方法验证了这种新方法的有效性。     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.     

Design considerations for soft embedded programmable logic cores

As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" rectangular layouts. We focus on an alternative approach for fine-grain programmability: vendors supply a synthesized RTL version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers in terms of speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or SoC. When the required amount of programmable logic is small, this ease of use may be more important than the increased overhead. This paper presents two synthesized "soft" programmable logic core architectures and describes their associated place and route issues. We compare the two architectures to each other, and to a "hard" programmable logic core. We also show how these cores can be made more efficient by creating a nonrectangular architecture, an option not usually available to "hard" core vendors. Finally, a proof-of-concept integrated circuit containing one of these cores is described.     

基于JTAG标准的电流模A/D转换器可测试性设计

边界扫描技术是一种重要的可测试性设计（DFT）技术，该技术不仅可以测试芯片或PCB之间的管脚连接是否存在故障，还可以测试芯片的逻辑功能。JTAG标准是该技术的相关协议。以JTAG标准为基础，结合一款新型电流模A／D转换器的测试需求，提出了一种基于JTAG标准的扫描测试结构，完成对电流模A／D转换器的参数测试。     

A finite state machine based fault tolerance technique for sequential circuits

With technology advancement at the nanometer scale, systems became more subjected to higher manufacturing defects and higher susceptibility to soft errors. Currently, soft errors induced by ion particles are no longer limited to a specific field such as aerospace applications. This raises the challenge to come up with techniques to tackle soft errors in both combinational and sequential circuits. In this work, we propose a finite state machine (FSM) based fault tolerance technique for sequential circuits. The proposed technique is based on adding redundant equivalent states to protect few states with high probability of occurrence. The added states guarantee that all single faults occurring in the state variables of highly occurring states or in their combinational logic are tolerated. The proposed technique has minimal area overhead as only few states need protection.     

Time redundancy and gate sizing soft error-tolerant based adder design

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.