高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.     

高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.     

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS(SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment,a TCAD simulation and a charge pumping test.For different stress conditions,degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented.Then the effect of various doses of n-type drain drift(NDD) region implant on R_(on) degradation is investigated.Experimental results show that a lower NDD dosage can redu...     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

Hot carrier effects on analog performance of N- and P-MOSFET's withoxynitride gate dielectrics

In this paper we report the impact of hot-carrier stress on analog performance of n- and p-MOSFET's with conventional oxide, NH₃-nitrided oxide (RTN) and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics. Changes due to hot-carrier stress in crucial analog parameters viz., drain output resistance, voltage gain, and input offset voltage of a source coupled differential MOSFET pair are investigated. Results show that RTN/RTO gate dielectrics suppress degradation of analog parameters in n-MOSFET's but increase it slightly in p-MOSFET's, as compared to conventional oxide MOSFET's     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET’S

The hot-carrier-induced oxide regions in the front and back interfaces are systematic-cally studied for partially depleted SOI MOSFET‘s .The gate oxide properties are investigated for channel hot-carrier effects.The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection,i.e.the maximum gate current, maximum substrate current and parasitic bipolaf transistor action.Experiments show that PMOSFET‘s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET‘s degradation is caused by hot holes.This paper reports for the first time that the electric characteristics of NMOSFET‘s and PMOSFET‘s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.     

Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high     

阶梯栅氧结构的NLDMOS热载流子效应研究

本文对一种新型的阶梯栅氧结构的NLDMOS（Step Gate Oxide NLDMOS , SG-NLDMOS）的热载流子效应进行了研究。采用直流电压应力实验、TCAD仿真、电荷泵测试等方法,对退化现象进行了分析,并提出了退化机制。然后研究了漂移区注入剂量对器件热载流子效应的影响,结果表明低的漂移区注入剂量可以更有效地减小器件导通电阻的退化。     

A new insight into the degradation behavior of the LDD N-MOSFETduring dynamic hot-carrier stressing

A new degradation behavior of LDD N-MOSFETs during dynamic hot-carrier stress is presented. Increased degradation occurs during the gate pulse transition, and involves hot-hole injection that initially begins in the oxide-spacer region, and later propagates to the channel region. Experimental results clearly show that increased degradation of the linear drain current and transconductance is mainly due to hole-induced interface traps in the oxide-spacer region. Electron trapping at hole-induced oxide defects, on the other hand, is mainly responsible for the enhanced threshold voltage shift in the late stage, when hole injection coincides with electron injection in the channel region     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.     

Hot-carrier effects on gate-induced-drain-leakage (GIDL) current inthin-film SOI/NMOSFET's

The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Experimental evidence for nonlucky electron model effect in 0.15-/spl mu/m NMOSFETs

It is shown that in 0.15-/spl mu/m NMOSFETs the device lifetime under channel hot-carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-/spl mu/m NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to increased interface state generation by the movement of the maximum impact ionization site from the lightly doped drain (LDD) diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. This paper provides experimental evidence for the non-LEM effect by comparing the degradation characteristics and the maximum impact ionization sites as a function of gate oxide thickness and gate length.     

Anomalous turn-on voltage degradation during hot-carrier stress inpolycrystalline silicon thin-film transistors

In this letter, we present experimental data showing that hot-carrier stress in laser annealed polycrystalline silicon thin-film transistors provokes an anomalous turn-on voltage variation. Although under various hot-carrier stress intensities the maximum transconductance degradation shows the same power-time dependent law, turn-on voltage can exhibit different behaviors. This observation lead to the conclusion that turn-on voltage depends on two different degradation mechanisms: injection of hot carriers into the gate oxide and degradation of grain boundaries. We show that these two mechanisms may be distinguished since they obey different power-time dependent laws as a function of stress duration     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

A compact pre- and post-stress I-V model for submicrometerburied-channel pMOSFETs

In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.