Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process

This work describes and discusses fast wafer level reliability (fWLR) Monitoring as a supporting procedure on productive wafers to achieve stringent quality requirements of automotive, medical and/or aviation applications. Examples are given for the various reliability topics: dielectrics, devices, metallisation, plasma charging with respect to required test structures, stress methods and data analysis. Application areas of fWLR are highlighted and limitations considered. Further aspects such as relevant reliability parameters, sampling strategies and out of control action plans are discussed.     

Automation and fab concepts for 300 mm wafer manufacturing

The introduction of 300 mm wafers into integrated circuit manufacturing will affect the design of the fabs. This paper covers the expectations of IC manufacturers and the progress in technology with respect to the fab itself and automation systems. The fab design is affected by the future use of closed wafer carriers, a consequent automation strategy, new challenges in contamination control, and the increased importance of environmental aspects. It will be described how these factors influence the fab design and the status of the discussed technologies.     

Contact etch process optimization for RF process wafer edge yield improvement

Radio-frequency (RF) process products suffer from a wafer edge low yield issue, which is induced by contact opening. A failure mechanism has been proposed that is based on the characteristics of a wafer edge film stack. The large step height at the wafer’s edge leads to worse planarization for the sparse poly-pattern region during the inter-layer dielectric (ILD) chemical mechanical polishing (CMP) process. A thicker bottom anti-reflect coating (BARC) layer was introduced for a sparse poly-pattern at the wafer edge region. The contact open issue was solved by increasing the break through (BT) time to get a large enough window. Well profile and resistance uniformity were obtained by contact etch recipe optimization.     

Strategy and metrics for wafer handling automation in legacysemiconductor fab

We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as well as overall fab goals and attitudes that are required to achieve full wafer handling automation. After considering several approaches to staged fab automation, we selected an approach which eliminated all manual handling within specific fab modules, completing the automation within one group of modules before embarking on another module set. In this way, we limited both the initial scope and cost of the project while preparing to leverage its initial successes. This paper summarizes the methodology and metrics found useful for preparing the fab for change, executing the change, and successfully managing the overall project     

Using EWMA control schemes for monitoring wafer quality in negative binomial process

The traditional control chart for nonconformities (called C control chart) assumes that process nonconformities follow a Poisson distribution. In actuality, however, the occurrence of nonconformities does not always observe Poisson distribution. For example, when nonconformities of wafers have clustering phenomenon in semiconductor production process, the process control based on Poisson distribution always underestimates the true average nonconformities and process variance. If the compound Poisson process is taken as the basis for process control, the quality feature could be described more accurately. When the process has minor variation, the sensitivity of the exponentially weighted moving average (EWMA) control chart is higher than the C control chart and more accurately reflects the current situation of the process on the control chart. Hence, this study considers Poisson-Gamma compound distribution for the failure mechanism, and takes the Markov chain approach to calculate the average run length produced by the EWMA control chart with different design parameters. Moreover, the EWMA control chart based on Poisson-Gamma compound distribution was constructed and actual data from a wafer plant were employed to illustrate the operation of the model. This study could be useful for detecting minor process variations in wafer plants and improving the process quality.     

Simulation tool for design and management optimization of automatedinterbay material handling and storage systems for large wafer fab

The ever-increasing need to introduce in Wafer Fab automated handling and storage systems, requires reliable design and performance analysis tools. In this paper a simulation model, able to represent both the handling and storage devices and the Wafer Fab production progress, is presented. The process dynamic is approached by generalized probability density functions linked only to global process parameters (i.e. throughput time, theoretical cycle times), that may be a priori known. The methodology is tested with reference to a large Wafer Fab recently installed in Italy by Texas Instruments     

Plasma process induced damage detection by fast wafer level reliability monitoring for automotive applications

Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed.     

A method for AlCu interconnect electromigration performance predicting and monitoring

The physical properties of (bottom)Si/SiO₂/Ti(top) and (bottom)Si/SiO₂/Ti/TiN/Al(0.5 wt.% Cu)(top) structures by different processes were compared and studied. The resistivities of thin Ti films and the reflectivities of thin Al alloy films were found to correlate to their microstructure as well as the mean time to fail (MTTF) in electromigration (EM) testing. A method to predict and monitor the EM performance of the AlCu interconnects was proposed.     

Integration and characterization of gas cluster processing for copper interconnects electromigration improvement

Basic physical properties as well as electrical and reliability performance of Infusion™ processing were evaluated. This approach, proposed as an alternative to CuSiN and electrolessly deposited Co-alloys, was shown to join the benefits of these two techniques without well-known associated drawbacks. Indeed, it is a uniform process, acting as an efficient Cu diffusion barrier, which does not require specific integration development. Different processes were introduced in a multi-level interconnect stack using ULK/USG stack as IMD, showing excellent electrical properties, and three times electromigration time-to-failure improvement with respect to standard SiCN barrier. However, it was shown that existing process conditions lead to some introduction of N atoms into ULK dielectric, showing there is still some room for process optimization in architectures using un-capped ULKs, to keep the benefits of EM improvement and aggressive effective dielectric constant.     

2-Step algorithm for automatic alignment in wafer dicing process

In this study, automatic alignment algorithm was developed for wafer dicing. Dual inspection method was applied for wafer alignment. The algorithm was derived from inspection data and geometric relations on machine coordinate. The algorithm calculated compensation value which minimized x, y, θ errors. Control strategy was designed according to characteristics of each axis. In experiment, standard position was defined with golden device. When working device was put on stable, it was aligned and moved by compensation value. Alignment error were inspected to check accuracy and precision of the algorithm. Average error was sub-pixel level for y axis on vision coordinate.     

Planning wafer allocation for CMOS process development. Anonparametric approach

In this paper, we present techniques that can be used to answer the following two questions: (1) how many wafers need to be allocated per treatment to detect a given difference in a device performance metric and (2) how can one determine if a given treatment significantly improved a performance metric? The approach presented here does not make any assumptions regarding the shape of the distribution or the spatial dependency structure for the within-wafer performance measurements and remains applicable for a variety of performance metrics, such as mean, variance, and median. The analysis method can be used in decisions regarding the appropriateness of allocating half or quarter wafer splits to a treatment. Furthermore, the approach allows us to evaluate and compare within-wafer sampling strategies for comparing performance metrics from competing flows     

A wafer level monitoring method for plasma-charging damage usingantenna PMOSFET test structure

A novel monitoring method for plasma-charging damage is proposed. This method performs a quick and accurate evaluation using antenna PMOSFET. It was found that not only hot-carrier (HC) lifetime but transistor parameters such as initial gate current and substrate current were changed according to the degree of plasma-charging damage. However, the present work suggests that monitoring the shift of drain current after a few seconds of HC stress is a more accurate method to indicate plasma-charging damage. The monitoring method using the present test structure is demonstrated to be useful for realizing highly reliable devices     

An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.     

A versatile, via terminated electromigration test structure for various stress modes used during fast wafer level reliability (fWLR) testing

A multipurpose electromigration (EM) test structure designed for advanced fast wafer level reliability (WLR) tests is described in this work. It is shown that different failure location and failure modes can be detected electrically by this test structures which is beneficial for early technology development as well as productive in-line monitoring. Highly accelerated WLR tests use the metal self-heating effect for temperature stress acceleration. It is shown here that the design of interconnects with respect to the critical metal line and the periphery of the tested metal line has a large impact on the stress temperature. A carefully designed test structure guarantees the ability to test for different EM failure modes (upstream, downstream). The presented experimental data focuses on the investigation of different process splits.     

Analytic approximations for multiserver batch-service workstationswith multiple process recipes in semiconductor wafer fabrication

This study extends previous results for batch-service workstations to batch-service/batch-lot workstations with multiple process recipes, e.g., diffusion operations in semiconductor manufacturing. The model considered herein explicitly considers the existence of a manufacturing operation associated with multiple process recipes in the semiconductor factory. Consequently, the revised balance equations are submitted and an improved approximation is presented for this case. Based on a comparison with simulation results, this new approximation is shown to be superior to the previously developed analytical approaches. This new approximation is especially strong in cases where the number of process recipes grows, system traffic intensity is moderate, and arrival rate of each recipe is nearly the same     

Ultrasonic sensor for photoresist process monitoring

An ultrasonic sensor has been developed to monitor photoresist processing in situ, during semiconductor manufacturing. Photoresist development, pre-exposure bake, and post-exposure bake were monitored for the Shipley 1800 series I-line resists, and the pre-exposure bake of Shipley APEX-E deep-uv (DUV) resist was monitored as well. Development monitoring was achieved by measuring thickness changes in the resist as it was removed. Data regarding dependence of development rate on exposure dose was obtained for the I-line resist with exposure doses varying from 20 to 68 mJ/cm². Measurements showed an increase in average development rate from 0.04 to 0.155 μm/s, with the rate leveling off at around 55 mJ/cm². Pre-exposure bake monitoring results demonstrated the ability of the sensor to measure the glass transition temperature of the resist film during prebake as well as the ability to invert out the elastic constants of the film using reflection theory. The glass transition temperature (T_g) is an important parameter in both the pre- and post-exposure bakes and therefore could be useful in monitoring these processes. Results of pre-exposure bake T_g measurements are presented for both-I-line and DUV resists. The glass transition temperature during prebake was found to be higher for the DUV resist than for the I-line series. The I-line resist post-exposure bake measurement of glass transition temperature confirmed the reported T_g of 118°C for the I-line novolac resin. The multiple uses of this sensor make it suitable for integration into a manufacturing setting     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

Experimental analysis and optimization of a photo resist coating process for photolithography in wafer fabrication

This investigation is applied the Taguchi method and combination the analysis of variance (ANOVA) to the photo resist (PR) coating process for photolithography in wafer manufacturing. Plans of experiments via nine experimental runs are based on the orthogonal arrays. In this study, the thickness mean and the uniformity of thickness of the PR are adopted as the quality targets of the PR coating process. This partial factorial design of the Taguchi method provides an economical and systematic method for determining the applicable process parameters. Furthermore, the ANOVA prediction of the thickness mean and the uniformity of thickness for the PR has been applied in terms of the PR temperature, chamber humidity, spinning rate, and dispensation rate by means of the designs of experiments (DOE) method. The PR temperature and the chamber humidity are found to be the most significant factors in both the thickness mean and the uniformity of thickness for a PR coating process. Finally, the sensitivity study of optimum process parameters was also discussed.