A fault simulation method: Parallel pattern critical path tracing

We present a fast fault simulation algorithm for combinational circuits which combines parallel pattern evaluation and critical path tracing. When the number of faults is large, our algorithm exploits the full advantages of critical path tracing. As fault dropping progresses, the overhead for critical path tracing surpasses its advantages. On the other hand, the efficiency of Parallel Pattern Single Fault Propagation (PPSFP) increases rapidly since relatively few undetected faults remain, and they tend to be inactive. To avoid the overhead of critical path tracing and achieve the advantages of PPSFP, dynamic update of node classes is used to produce a smooth transition from critical path tracing to PPSFP. By using this approach, we get high performance for both small and large numbers of test patterns. Also, preprocessing related to structure analysis is avoided while achieving almost all of its advantages.This work was supported in part by National Science Foundation grant MIP-9003292.     

Performance analysis of minimal path fault tolerant routing in NoC

Occurrence of faults in Network on Chip (NoC) is inevitable as the feature size is continuously decreasing and processing elements are increasing in numbers. Faults can be revocable if it is transient. Transient fault may occur inside router, or in the core or in communication wires. Examples of transient faults are overflow of buffers in router, clock skew, cross talk, etc.. Revocation of transient faults can be done by retransmission of faulty packets using oblivious or adaptive routing algorithms. Irrevocable faults causes non-functionality of segment and mainly occurs during fabrication process. NoC reliability increases with the efficient routing algorithms, which can handle the maximum faults without deadlock in network. As transient faults are temporary and can be easily revoked using retransmission of packet, permanent faults require efficient routing to route the packet by bypassing the nonfunctional segments. Thus, our focus is on the analysis of adaptive minimal path fault tolerant routing to handle the permanent faults. Comparative analysis between partial adaptive fault tolerance routing West-First, North-Last, Negative-First, Odd Even, and Minimal path Fault Tolerant routing (MinFT) algorithms with the nodes and links failure is performed using NoC Interconnect RoutinG and Application Modeling simulator (NIRGAM) for the 2D Mesh topology. Result suggests that MinFT ensures data transmission under worst conditions as compared to other adaptive routing algorithms.     

Two-dimensional analysis of a BiNMOS transistor operating at 77 Kusing a modified PISCES program

The authors present a detailed two-dimensional numerical simulation study on the steady-state and turn-on transient behavior of a BiNMOS device operating at 77 K using PISCES-2B with modified low-temperature models. It is shown that the switching speed of the BiNMOS device, which is designed for operation at room temperature, is degraded for low-temperature operation. The BiNMOS device structure and the low-temperature device models for the two-dimensional (2D) device simulator are described, following by the steady-state and the transient analysis of the BiNMOS device. The turn-on transient performance of the BiNMOS device shows that, at 77 K, the switching time, which is determined by the load-related delay and the intrinsic delay of the bipolar device, increases about 45% from its 300 K value for an output load of 0.1 pF/μm     

Quantum-well resonant tunneling bipolar transistor operating at room temperature

The first resonant tunneling bipolar transistor (RBT) is reported. The AlGaAs/GaAs wide-gap emitter device, grown by molecular beam epitaxy (MBE), contains a GaAs quantum well and two AlAs barriers between the emitter and the collector. In the common emitter configuration, when the base current exceeds a threshold value, a large drop in the collector current (corresponding to a quenching of the current gain β) is observed at room temperature, along with a pronounced negative conductance as a function of the collector-emitter voltage. These striking characteristics are caused by the quenching of resonant tunneling through the double barrier as the conduction band edge in the emitter is raised above the bottom of the first quantized subband of the well. Single-frequency oscillations are observed at 300 K. The inherent negative transconductance of these new functional devices is extremely valuable for many logic and signal processing applications.     

Model of a metal-oxide-silicon transistor operating in the saturation region

The output resistance of an m.o.s. transistor operating in the saturation region is studied experimentally and theoretically. New experimental properties of the `resistance?current? product are described. A model is proposed in which the structure is divided into two sections. In the source section, a gradual length approximation is assumed, taking into account the mobility?field dependence; while in the drain section, the mobile-carrier charge is included in the `equivalent doping?. The continuity conditions between the two regions are described. Good agreement is found between the theory and the experimental results.     

Measurement-based evaluation of operating system fault tolerance

The authors demonstrate a methodology for evaluating the fault-tolerance characteristics of operational software and illustrate it through case studies of three operating systems: the Tandem GUARDIAN fault-tolerant system, the VAX/VMS distributed system, and the IBM/MVS system. Based on measurements from these systems, software error characteristics are investigated by analyzing error distributions and correlation. Two levels of models are developed to analyze the error and recovery processes inside an operating system and the interactions among multiple copies of an operating system running in a distributed environment. Reward analysis is used to evaluate the loss of service due to software errors and the effect of fault-tolerant techniques implemented in the systems     

A new fault current-sensing scheme for fast fault protection of the insulated gate bipolar transistor

A new fault current-sensing scheme employing the floating p-well for fast protection of the insulated gate bipolar transistor (IGBT) from the short-circuit faults is proposed and verified by employing 2D mixed mode simulation, based on the previous experimental results. The proposed floating p-well current-sensing scheme detects not the normal operating current but the fault current of the main IGBT by using the diode connected MOSFET and a resistor, when the short-circuit fault occurs. The diode-connected MOSFET eliminates the degradation of the forward voltage drop, because the floating p-well current does not flow under the normal operating condition due to the threshold voltage of the diode connected MOSFET. The proposed current sensor increases the protection speed without any additional delay time by the external blanking filter.     

A fuzzy model for path delay fault detection

A fuzzy model is proposed to analyze the effectiveness of test pairs targeting path delay faults. This model is accurate enough to rank nonrobust tests by accounting for conditions not considered in existing models. It remains fully consistent with the traditional test robustness analysis. Finally, it also provides a coverage metric to be used to rank whole test sets. The proposed model has been implemented in a logic level path delay fault simulator. Its accuracy has been validated, for a set of combinational benchmarks, by means of a Monte Carlo logic-level event-driven path delay fault simulator.     

On local transformations and path delay fault testability

Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered.Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced.Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a pattern to be searched and a matched subcircuit can be weakened to allow the application of local transformations more frequently.Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.This work was supported in part by DFG grants Be 1176/4-1, Be 1176/4-2 and SFB 124 VLSI Design Methods and Parallelism.     

MOS Pass transistor turn-off transient analysis

Errors induced by turn-off transients are one fundamental limit in precision switched capacitor circuits. This paper presents detailed pass transistor turn-off transient analysis. Conventional single-lump models which assume quasi-static operation can introduce substantial errors for high-speed analog applications. New distributed and two-lump models have been constructed to analyze pass transistor turn-off transients in the diffusion mode of operation. A pass transistor test chip including a new selectively doped pass transistor approach has been designed, fabricated, and tested to verify the transient analysis. Measured performance of the nonuniformly doped pass transistors shows advantages in reducing transient charge errors.     

Optimization of the operating point of a vertical-cavitysurface-emitting laser

The wall-plug efficiency of a vertical-cavity surface-emitting laser is investigated. The optimum current which produces a maximum wall-plug efficiency is derived when the mirror reflectivity is fixed and the series resistance and parasitic leakage current are taken as variable parameters. The results are compared with experimental data. The optimum reflectivity in terms of both output power and wall-plug efficiency is determined for both unstrained and strained quantum lasers with fixed supply current and series resistance as a parameter. Temperature is also considered as a variable     

Multiple fault analog circuit testing by sensitivity analysis

Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit modeling and testing. The circuit modeling is based on first-order sensitivity computation. The testability of the circuit is analyzed by the multiple-fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing catastrophic and soft faults. Some experimental results are presented for simple models as well as multiple-fault models.     

Multiple-state resonant-tunneling bipolar transistor operating atroom temperature and its application as a frequency multiplier

A resonant-tunneling bipolar transistor with two peaks in the direct as well as in the transfer characteristics is presented. The multiple peaks are obtained by sequentially quenching resonant tunneling through the ground states of a series of double-barrier quantum wells, placed in the emitter of a Ga_0.47In_0.53As-Al_0.48In_0.52 As bipolar transistor, thus obtaining nearly equal peak currents and peak-to-valley ratios. The transistor exhibits current gain of about 70 at room temperature and 200 at 77 K. Peak-to-valley current ratios at room temperature and at 77 K are as high as 4:1 and 20:1, respectively. Frequency multiplication by factors of three and five has been demonstrated using the multiple-peak transfer characteristics of the transistor     

Delay fault testing of IP-based designs via symbolic path modeling

Predesigned blocks called intellectual property (IP) cores are increasingly used for complex system-on-a-chip (SoC) designs. The implementation details of IP cores are often unknown or unavailable, so delay testing of such designs is difficult. We propose a method that can test paths traversing both IP cores and user-defined blocks, an increasingly important but little-studied problem. It models representative paths in IP circuits using an efficient form of binary decision diagram (BDD) and generates test vectors from the BDD model. We also present a partitioning technique, which reduces the BDD size by orders of magnitude and makes the proposed method practical for large designs. Experimental results are presented that show that it robustly tests selected paths without using extra logic and, at the same time, protects the intellectual contents of IP cores     

Multiple fault analog circuit testing by sensitivity analysis

Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit modeling and testing. The circuit modeling is based on first-order sensitivity computation. The testability of the circuit is analyzed by the multiple-fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing catastrophic and soft faults. Some experimental results are presented for simple models as well as multiple-fault models.     

故障树最小割集和最小路集在火箭故障诊断中的应用

基于提高火箭故障诊断效率的目的,采用故障树分析原理,结合火箭故障的诊断实际,研究了一种基于故障树最小割集和最小路集的火箭故障快速诊断决策方案。为系统的故障源搜寻提供了具体有效的测试步骤。并给出了应用实例。     

Heat transfer analysis of beam-lead transistor chip

The program package which is applicable to solve problems of heat transfer in transistors or integrated-circuit chips or in their stems has been developed with a three-dimensional lumped network model. The thermal resistances of beam-lead transistors calculated with this program are found to be in good agreement with the observed values. For the better design of beam-lead devices, thermal resistances are evaluated with this program for various geometries of the chips and for the passivation films of 1-micron thick SiO2, 2-micron SiO2, and 0.2-micron Al2O3or Si3N4on 1-micron SiO2. The results calculated indicate that the thermal resistance is mainly dependent on the thickness of electroplated Au in the beam-lead structure, and that the heat dissipation is especially sensitive to the distance, which is measured along the beam lead from the chip edge to the nearest end of the joining part of the beam lead to the metallized conductor on the ceramic stem.