Emerging interconnects: a state-of-the-art review and emerging solutions

Aluminium was a primary material for interconnection in integrated circuits (ICs) since their inception. Later, copper was introduced as interconnect material which has better metallic conductivity and resistance to electromigration. As the aggressive technology scaling continues, the copper resistivity increased because of size effects, which causes increase in delay, power dissipation and electromigration. The need to reduce the resistor-capacitor??????? delay, dynamic power utilisation and the crosstalk commotion is as of now the fundamental main impetus behind the presentation of new materials. The purpose of this paper is to do a survey of interconnect material used in IC from introduction of ICs to till date. This paper studies and reviews new materials available for interconnect application which are optical interconnects, carbon nanotube (CNT), graphene nanoribbons (GNRs) and silicon nanowires which are alternatives to copper. While doing a survey of interconnect material, it is found that multiwalled CNTs, multilayer GNR and mixed CNT bundles are promising candidates and are ultimate choice that can strongly address the problems faced by copper but on integration basis copper would last for coming years.     

Technology and reliability constrained future copper interconnects.I. Resistance modeling

A realistic assessment of future interconnect performance is addressed, specifically, by modeling copper (Cu) wire effective resistivity in the light of technological and reliability constraints. The scaling-induced rise in resistance in the future may be significantly exacerbated due to an increase in Cu resistivity itself, through both electron surface scattering and the diffusion barrier effect. The impact of these effects on resistivity is modeled under various technological conditions and constraints. These constraints include the interconnect operation temperature, the effect of copper-diffusion barrier thickness and its deposition technology, and the quality of the interconnect/barrier interface. Reliable effective resistivity trends are established at various tiers of interconnects, namely, at the local, semiglobal, and global levels. Detailed implications of the effect of resistivity trends on performance are addressed in the second part of this work     

柠檬酸在钴基铜互连CMP及后清洗的研究进展

钴(Co)具有较低的电阻率、良好的热稳定性、与铜(Cu)粘附性好等优点,可以替代钽(Ta)成为14 nm以下技术节点集成电路(IC) Cu互连结构的新型阻挡层材料。化学机械抛光(CMP)是唯一可以实现Cu互连局部和全局平坦化的方法,也是决定Co基Cu互连IC可靠性的关键技术。柠檬酸含有羟基,在电离后对金属离子有较强的络合作用,成为Co基Cu互连CMP及后清洗中的主要络合剂。文章评述了柠檬酸在Cu互连CMP及后清洗中的应用和研究进展,包括柠檬酸对Cu/Co去除速率选择比、Co的表面形貌以及Co CMP后清洗中Co表面残留去除等方面的影响,并展望了络合剂及Cu互连阻挡层CMP的发展趋势。     

Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects. This paper discusses the modeling of nanotube bundle resistance for on-chip interconnect applications. Based on recent experimental results, the authors model the impact of nanotube diameter on contact and ohmic resistance, which has been largely ignored in previous bundle models. The results indicate that neglecting the diameter-dependent nature of ohmic and contact resistances can produce significant errors. Using the resistance model, it is shown that SWCNT bundles can provide up to one order of magnitude reduction in resistance when compared with traditional copper interconnects depending on bundle geometry and individual nanotube diameter. Furthermore, for local interconnect applications, an optimum nanotube diameter exists to minimize the resistance of the carbon nanotube bundle.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

多层空气隙Cu互连结构耦合电容的优化

随着超大规模集成电路特征尺寸不断缩小,多层cu互连之间的RC延迟成为一个越来越严重的问题.由于低介电常数(low-k)材料配合空气隙(air gap)结构可用于降低Cu互连导线间的耦合电容从而改善RC延迟特性,建立了单层和多层空气隙Cu互连结构的有限元分析模型,以研究空气隙结构尺寸与互连介质等效介电常数的关系.结果表明,在单层空气隙Cu互连结构中,通过增加互连导线间空气隙的结构尺寸可以减小Cu互连结构中的耦合电容,进而改善RC延迟特性;在多层空气隙Cu互连结构中,通过改变IMD和ILD中空气隙的尺寸结构可以得到RC延迟性能优化的多层空气隙Cu互连结构.     

Contact and via structures with copper interconnects fabricatedusing dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi₂/n⁺-Si, CoSi₂/p⁺-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO₂ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O₂ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10^-6Ω-cm² or less. A specific contact resistivity value of 1.5×10^-8Ω-cm² was measured for metal/metal contacts     

铜互连新型阻挡层材料的研究进展

铜互连阻挡层材料起到防止铜与介质材料发生扩散的重要作用。因此,阻挡层材料需要满足高稳定性、与铜和介质材料良好的粘附性以及较低的电阻。自1990年代以来,氮化钽/钽(TaN/Ta)作为铜的阻挡层和衬垫层得到了广泛的应用。然而,随着晶体管尺寸微缩,互连延时对芯片速度的影响越来越重要。由于TaN/Ta的电阻率高且无法直接电镀铜,已经逐渐难以满足需求。文章综述了铜互连阻挡层材料的最新进展,包括铂族金属基材料、自组装单分子层、二维材料和高熵合金,以期对金属互连技术的发展提供帮助。     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

Modelling of thermal failure of metallic interconnects under electrostatic discharge transients

Temperature dependence of metal electrical resistivity is taken into account in modelling of thermal failure of metallic interconnects under electrostatic discharge (ESD) events. SPICE-based electro-thermal modelling is used to calculate the maximum temperature rise in the interconnect during stress. New ESD design guidelines for interconnects, based on the threshold temperature of latent failure, are proposed to optimise the interconnect width.     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

Mono- or bi-layer metallic single-wall carbon nanotube interconnects have lateral capacitances more than four times smaller than those of copper interconnects. The resistance and time-of-flight of these monolayer nanotubes would be larger than that of copper interconnects. For short lengths, however, driver resistance is quite dominant, and latency is determined by interconnect capacitance. Monolayer nanotube interconnects are therefore promising candidates for local interconnects. The average capacitance per unit length of these nanotube interconnects can be 50% smaller than that of copper interconnects and that leads to significant saving in power dissipation.     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects.      

Technology and reliability constrained future copper interconnects.II. Performance implications

For pt. I see ibid., vol.49, no.4, pp.590-7 (2002). This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity     

Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit

Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. In this paper, we analyze the performances of a prototype 0.25-$muhbox{m}$ CMOS digital integrated circuit with select horizontal multiwall CNT (MWCNT) interconnects. Some local interconnect wires of the prototype chip were implemented, during a post-CMOS assembly process, by single 14-$muhbox{m}$ -long metallic MWCNT with 30-nm diameter, representative of future requirements for local interconnects. We evaluate the merits and challenges of MWCNT interconnects in a realistic silicon integrated-circuit environment. We experimentally extract the subnanosecond delays of these wires to quantitatively benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, as well as with the expected performances of scaled copper wires. Finally, we discuss the origin of the discrepancies between our experimental results and the modeling projections.      

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Highly Conductive,Flexible, Polyurethane‐Based Adhesives for Flexible and Printed Electronics

Flexible interconnects are one of the key elements in realizing next‐generation flexible electronics. While wire bonding interconnection materials are being deployed and discussed widely, adhesives to support flip‐chip and surface‐mount interconnections are less commonly used and reported. A polyurethane (PU)‐based electrically conductive adhesive (ECA) is developed to meet all the requirements of flexible interconnects, including an ultralow bulk resistivity of ≈1.0 × 10^?5 Ω cm that is maintained during bending, rolling, and compressing, good adhesion to various flexible substrates, and facile processing. The PU‐ECA enables various interconnection techniques in flexible and printed electronics: it can serve as a die‐attach material for flip‐chip, as vertical interconnect access (VIA)‐filling and polymer bump materials for 3D integration, and as a conductive paste for wearable radio‐frequency devices.     

超高速光互连系统级封装技术前沿研究

光互连系统级封装技术是用光互连在封装尺度上代替铜互连,以突破目前芯片间通信低速度瓶颈。超高速光互连系统级封装的目标是开发出可集成光子收发器,并嵌入到现代尖端的系统级封装中(SiP)中,以提高并行计算系统的数据传输效率或速度。文章介绍了超高速光互连系统级封装关键技术及前沿研究情况,通过分析IMEC、Intel、BAE系统公司等研究机构的开发现状和技术发展路线,论述了光互连SiP关键技术的发展趋势。     

片内光通信技术综述

在纳米工艺水平下,传统的铜线互连已经很难满足集成电路芯片在延迟、带宽、功耗等方面的要求,片内通信问题已经成为集成电路设计的瓶径.文中根据片内光器件集成技术的最新进展,介绍了采用片内光互连代替电互连的最新技术及其性能方面的优势.文中重点总结了片内光互连的三种典型应用.首先,介绍了片内光时钟分布网络;其次,从应用的角度分析了光电总线结构相对于单纯电总线在性能上的提升;最后,介绍了一种新的片上光网络,它集成了片内电的包交换控制网络和宽带电路交换光网络.仿真和实验结果表明,光互连能够为高集成度纳米级芯片提供高带宽、低延迟,小功耗的片内通信服务.