Interfacial layer optimization of high-k/metal gate stacks for low temperature processing

Understanding the requirements for obtaining high mobility gate stacks in a low temperature process is crucial for enabling a low temperature integration flow. A low temperature integration scheme may be necessary for higher-k dielectrics (k > 25) or for extremely scaled devices (<15 nm node). This paper demonstrates that nitrogen free interfaces are required for high mobility gate stacks in a low temperature (600 °C) process flow.     

Theoretical analysis of high-k dielectric gate stacks

Density functional theory (DFT) has proved to be a useful tool in engineering of emerging research devices. At the nanoscale, and particularly when novel materials are involved, it provides not only the fundamental understanding of the microscopic physics governing the behavior of a system, but often can give quantitative results that can be directly used in process development. In this paper we briefly review the recent applications of DFT in the area of the advanced gate stack materials engineering     

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.     

Recent advances and current challenges in the search for high mobility band-edge high-k/metal gate stacks

Continued miniaturization of the different physical elements of a Si MOSFET required in order to attain higher transistor performance and greater economies of scale have spurred the need for significant materials innovations. This is most apparent in the search for the ideal high-k/Metal Gate stack that would replace conventional SiON/Poly-Si gate stacks. In this paper, we will review some of the recent advances and remaining challenges for high-k/Metal Gate stacks. It is shown that significant progress has been made towards improving electron mobility in HfO₂/Metal Gate stacks by a combination of high temperature processes, nitrogen free interfaces and optimized metal deposition processes which result in mobility values competitive with SiON/Poly-Si. In addition by inserting nanoscale layers that comprise strongly electropositive gp. IIA and IIIB elements in between the HfO₂and metal electrode stack have resulted in high mobility, band-edge aggressively scaled High-k/Metal Gate stacks. While much progress has been made with nMOSFET stacks, it will also be shown that a number of roadblocks remain with obtaining a similar solution for pMOSFET stacks, primarily due to the presence of thermally activated oxygen vacancies that induce large negative threshold voltage shifts towards midgap in HfO₂/high workfunction metal stacks.     

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes

We present a novel metal gate/high-k complementary metal–oxide–semiconductor (CMOS) integration scheme with symmetric and low threshold voltage (V_th) for both n-channel (nMOSFET) and p-channel (pMOSFET) metal–oxide–semiconductor field-effect transistors. The workfunction of pMOSFET is modulated by oxygen in-diffusion (‘oxygenation’) through the titanium nitride metal gate without equivalent oxide thickness (EOT) degradation. A significant V_th improvement by 420 mV and an aggressively scaled capacitance equivalent thickness under channel inversion (T_inv) of 1.3 nm is achieved for the pFET by using a replacement process in conjunction with optimized oxygenation process. Immunity of nMOSFET against oxygenation process is demonstrated.     

高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices

In this work, we investigated the effect of so-called WF (Work Function) setting anneal (high temperature annealing on TiN/HfO₂ stack) on gate stack properties. It was found that intermixed layer created in-between TiN and HfO₂ during WF setting anneal has negative fixed charge and reduces pFET V_t (positive V_t shift). In addition, higher anneal temperature further reduces pFET V_t while keeping nFET V_t almost unchanged. This could be explained by passivation of oxygen vacancies in HfO₂ with diffused oxygen from TiN layer. By combining these effects, one can further push effective work function towards valence band edge which enables wider coverage of transistor V_t option.     

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.     

超薄EOT高K金属栅结构中串联电阻效应对瞬时击穿特性的影响

本文研究了超薄EOT高K金属栅MOS电容结构的瞬时击穿特性。由于串联电阻效应的影响,MOS电容的瞬时击穿特性的面积依赖关系与理论推导不符。器件中的串联电阻可以通过对IV特性的FN拟合得到。在本文的器件结构中,经验证得到串联电阻主要是由于电极的不对称性引起的扩展电阻。本文提出一种采用串联模型对击穿分布特性进行修正的方法。修正后的瞬时击穿特性与面积的依赖关系符合泊松面积归一规律,这说明对于超薄EOT的高K金属栅结构,瞬时击穿的机制与时变击穿的机制相同,都是由缺陷产生过程导致的击穿过程。     

Top-TiN生长条件及TaN厚度对MOSCAP栅叠层有效功函数的影响

我们引入TaN/TiAl/top-TiN三层结构,通过变化TaN的厚度及top-TiN的生长条件来调节TiN-based金属栅叠层的有效功函数。实验结果显示：较薄的TaN和PVD-process生长的top-TiN组合可以得到较小的有效功函数(EWF),而较厚的TaN和ALD-process生长的top-TiN组合可以得到较大的有效功函数(EWF),文中EWF有从4.25eV to 4.56eV的变化。同时文中也给出了TaN厚度及top-TiN的生长条件调节有效功函数(EWF)的物理解释。与PVD-process在室温条件下生长TiN相比,ALD-process TiN是在400 ℃条件下生长的,400 ℃ ALD-process TiN 可以为整个工艺过程提供更多的热预算,从而促进更多的Al原子扩散进入top-TiN,导致扩散进入到bottom-TiN的Al原子数量减少。另外,厚的TaN也会阻止Al原子进入bottom-TiN。这些因素都减少了bottom-TiN中Al原子的数量,减弱了Al原子对有效功函数的调节作用,从而引起EWF的增加。     

Application of combinatorial methodologies for work function engineering of metal gate/high-κ advanced gate stacks

This paper uses combinatorial methodologies to investigate the effect of TaN-AlN metal gate electrode composition on the work function, for (TaN-AlN)/Hf-Si-O/SiO₂/Si capacitors. We demonstrate the efficacy of the combinatorial technique by plotting work function for more than thirty Ta_1-xAl_xN_y compositions, with x varying from 0.05 to 0.50. The work function is shown to continuously decrease, from about 4.9 to about 4.7 eV, over this range. Over the same range, oxide fixed charge is seen to go from about -2.5 × 10¹² cm⁻³ to about zero. The work functions reported here are about 0.1 eV higher than in a previous study, but are still about 0.2 eV smaller than required for PMOS device applications.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性研究

本文对后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性进行了研究。在加速应力电压和高温条件下,NMOSFET的阈值电压的退化与时间呈幂指数关系。然而幂指数随应力电压的增大而减小;在本文中,应力从0.6V到12V,幂指数则相应的由0.26减小到0.16。通过对应力前后器件的亚阈值特性分析,在应力过程中没有界面态产生。根据实验数据提取到数值为0.1eV的热激活能,表明偏压温度不稳定性是由栅介质中预先存在的陷阱俘获从衬底隧穿的电子造成的。恢复阶段的测试显示阈值电压的退化与对数时间呈线性关系,同时可以用确定的数学表达式来表明其与应力电压和温度之间的关系。     

Reduction of the anomalous VT behavior in MOSFETs with high-κ/metal gate stacks

This study investigates the impact of different nitridation processes on hafnium silicon oxynitride (HfSiON) dielectrics. It is demonstrated that the threshold voltage (V_T vs. L_g) behavior at short gate lengths is strongly impacted by the nitridation process, depending on the Hf/(Hf+Si) ratio and the HfSiON thickness. A Plasma nitridation in oxidizing ambient results in a modification of the dielectric that can explain the anomalous V_T behavior in devices integrated with hafnium-based dielectrics and metal gate. Reduction in anomalous V_T behavior and limited gate leakage is achieved by applying a thermal nitridation in a NH₃ ambient on Hf-rich silicon oxynitride.     

A novel approach to silicon gate CMOS device scaling

A new approach is reported for fabricating scaled Si-gate CMOS devices using medium temperature (?900° C) LPCVD deposited SiO₂ as the dielectric interlayer. The film can be deposited from 850 to 1000°C using a graded temperature profile and optimum pressure. A maximum of 100 wafers with 8% variation of thickness per run has been achieved using the process described in this paper. The medium-temperature LPCVD SiO₂ film exhibited step-coverage as good as the conventional low temperature PSG film. Since the new film requires no high temperature treatment, the convetional Si-gate CMOS diffusion process has been used to obtain the micron and submicron junction depths that are required to fabricate scaled CMOS devices. Such a processing approach, converting a 5–6 μm geometry CMOS process to a 3 μm geometry CMOS process, is described.     

Compensation of oxygen defects in La-silicate gate dielectrics for improving effective mobility in high-k/metal gate MOSFET using oxygen annealing process

Oxygen incorporation for compensation of oxygen defects is investigated with La-silicate dielectrics in directly contacted with the Si substrate. The amount of oxygen is controlled by the temperature of annealing in oxygen atmosphere (oxygen annealing) and the thickness of the gate electrode. The positive shift in flatband voltage (V_FB) by oxygen incorporation is an experimental evidence for defects compensation in La-silicate dielectrics. Optimum oxygen annealing provides the V_FB shift toward positive direction without increasing equivalent oxide thickness (EOT). Although the oxygen annealing degrades the interfacial property at La-silicate/Si interface, subsequent forming gas annealing (FGA) can recover the interfacial property. It is experimentally revealed that the positive V_FB shift of La-silicate dielectrics is stable even after subsequent FGA. The supplied oxygen in La-silicate is expected to maintain even after reducing process. Movement of Fermi level toward the Si valence band edge caused by oxygen incorporation is successfully observed by XPS. Moreover, no chemical reaction between La-silicate and Si substrate by oxygen annealing are confirmed from TEM observation and analyses of X-ray photoelectron spectra. It is experimentally demonstrated that effective hole mobility can be improved without increase in EOT by combination of oxygen annealing and FGA.     

An approach to statistical analysis of gate oxide breakdown mechanisms

A credible statistical algorithm is required to determine the parameters of the bimodal Weibull mixture distribution exhibited by the gate oxide breakdown phenomenon, consisting of extrinsic early-life defect-induced failures and intrinsic wear-out failure mechanisms. We use a global maximization algorithm called simulated annealing (SA) in conjunction with the expectation–maximization (EM) algorithm to maximize the log-likelihood function of multi-censored gate oxide failure data. The results show that the proposed statistical algorithm provides a good fit to the stochastic nature of the test failure data. The Akaike information criterion (AIC) is used to verify the number of failure mechanisms in the given set of data and the Bayes’ posterior probability theory is utilized to determine the probability of each failure data belonging to different failure mechanisms.