Enhancement in electrical performance of indium gallium zinc oxide-based thin film transistors by low temperature thermal annealing

We have studied the characteristics of transparent bottom-gate thin film transistors (TFTs) using In–Ga–Zn–O (IGZO) as an active channel material. IGZO films were deposited on SiO₂/Si substrates by DC sputtering techniques. Thereafter, the bottom-gate TFT devices were fabricated by depositing Ti/Au metal pads on IGZO films, where the channel length and width were defined to be 200 and 1000 μm, respectively. Post-metallization thermal annealing of the devices was carried out at 260, 280 and 300 °C in nitrogen ambient for 1 h. The devices annealed at 280 °C have shown better characteristics with enhanced field-effect mobility and high on–off current ratio. The compositional variation of IGZO films was also observed with different annealing temperatures.     

The use of hydrogen passivation to fabricate Schottky diodes for DLTS measurements of heavily-doped p+ Si

Schottky diodes were successfully fabricated on p⁺ Si for deep-level transient spectroscopy (DLTS) measurements by the use of hydrogen passivation of boron. Atomic hydrogen was introduced into the near-surface region of boron-doped (1 0 0) CZ Si crystals, which had a resistivity of about 0.01 Ω cm, at temperatures between room temperature and 300°C by exposure to a hydrogen plasma. Rectifying characteristics were obtained for fabricated Schottky contacts on hydrogenated samples. This was due to the carrier concentration decrease in the near-surface region by hydrogen passivation of boron. As the hydrogenation temperatures were increased, the decrease in carrier concentration was significant. Some results of DLTS measurements were given for fabricated diodes.     

Effect of annealing on photoluminescence of passivated porous silicon

Photoluminescence (PL) of annealed porous silicon (PS) without and with nitrogen passivation has been investigated. The un-nitridated PS emits intense blue and green light, while that with passivation, emits only blue light and its intensity increases obviously. It is found that the PL intensity of the nitrified PS decreases with increasing temperature from 300 °C to 700 °C, but increases drastically after annealing at 800 °C and 900 °C, which might be due to the formation of Si–N bonds that passivates the non-radiative centers (Si dangling bonds) on the surface of PS samples. However, the intensity of the un-nitridated PS decreases continuously with increasing temperature from 300 °C to 900 °C, which might be due to desorption of hydrogen.     

Determination of the average channel temperature of GaN MOSHFETs under continuous wave and periodic-pulsed RF operational conditions

We present a method to determine the average device channel temperature of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOSHFETs) in the time domain under continuous wave (CW) and periodic-pulsed RF (radiation frequency) operational conditions. The temporal profiles of microwave output power densities of GaN MOSHFETs were measured at 2 GHz under such conditions and used for determination of the average channel temperature. The measurement technique in this work is also being utilized to determine the thermal time constant of the devices. Analytical temporal solutions of temperature profile in MOSHFETs are provided to support the method. The analytical solutions can also apply to generic field effect transistors (FETs) with an arbitrary form of time-dependent heat input at the top surface of the wafer. It is found that the average channel temperature of GaN MOSHFETs on a 300 μm sapphire substrate with the output power of 10 W/mm can be over 400 °C in the CW mode while the average channel temperature of GaN MOSHFETs on a SiC substrate with the same thickness only reaches 50 °C under the same condition. The highest average channel temperature in a pulsed RF mode will vary with respect to the duty cycle of the pulse and type of the substrate.     

Junction temperature of QFN32 and 64 electronic devices subjected to free convection. Effects of the resin's thermal conductivity

The thermal state of the electronic devices used in many engineering fields must be controlled. The maximum temperature does not exceed the value recommended by the manufacturer to prevent a decrease of their reliability, malfunction or decommissioning. The junction temperature of the Quad Flat Non-Lead (QFN) device which often equips the electronic assemblies is affected by the thermal characteristics of its components, in particular the thermal conductivity of the molding compound (resin) used for the package encapsulation. This work deals with the QFN32 and QFN64 models widely used in the field of smart building. These devices may be tilted of any angle from the horizontal and vertical positions, depending on where they are located in the considered building. The packages located in small boxes are subjected to air natural convection. The 3D numerical approach based on the volume control method considers several configurations obtained by varying the generated power between 0.01 and 0.1 W by steps of 0.01 W, corresponding to the partial operation. The junction thermal state is determined for many values of the resin's thermal conductivity ranging between − 80% and + 100% of its average value and inclination of the devices varying between 0 and 90° (horizontal and vertical positions respectively) by steps of 15°. The results of the numerical solution are confirmed by thermal and electrical measurements carried out in situ on various prototypes. The deviation between measurements and calculations is low, ranging between − 3 and + 7%. New and accurate relationships are proposed, allowing to improve the thermal design of the QFN32 and QFN64 packages by determining their junction temperature for any combination of the considered generated power, tilt angle and thermal conductivity of the encapsulating resin. The control of the thermal aspect allows to enhance substantially the reliability of these widely used electronic devices.     

Study on the thermal stability of Ga-doped ZnO thin film: A transparent conductive layer for dye-sensitized TiO2 nanoparticles based solar cells

Generally, optoelectronic devices are fabricated at a high temperature. So the stability of properties for transparent conductive oxide (TCO) films at such a high temperature must be excellent. In the paper, we investigated the thermal stability of Ga-doped ZnO (GZO) transparent conductive films which were heated in air at a high temperature up to 500 °C for 30 min. After heating in air at 500 °C for 30 min, the lowest sheet resistance value for the GZO film grown at 300 °C increased from 5.5 Ω/sq to 8.3 Ω/sq, which is lower than 10 Ω/sq. The average transmittance in the visible light of all the GZO films is over 90%, and the highest transmittance is as high as 96%, which is not influenced by heating. However, the transmittance in the near-infrared (NIR) region for the GZO film grown at 350 °C increases significantly after heating. And the grain size of the GZO film grown at 350 °C after annealing at 500 °C for 30 min is the biggest. Then dye-sensitized TiO2 NPs based solar cells were fabricated on the GZO film grown at 350 °C (which exhibits the highest transmittance in NIR region after heating at 500 °C for 30 min) and 300 °C (which exhibits the lowest sheet resistance after heating at 500 °C for 30 min). The dye-sensitized solar cell (DSSC) fabricated on the GZO film grown at 350 °C exhibits superior conversion efficiency. Therefore, transparent conductive glass applying in DSSCs must have a low sheet resistance, a high transmittance in the ultraviolet–visible–infrared region and an excellent surface microstructure.     

Effect of annealing temperature on optical and electrical properties of lead sulfide thin films

Lead sulfide (PbS) thin films with 150 nm thickness were prepared onto ultra-clean quartz substrate by the RF-sputtering deposition method. Deposited thin films of PbS were annealed at different temperatures 100 °C, 150 °C, 200 °C, 250 °C and 300 °C. X-ray diffraction pattern of thin films revealed that thin films crystallized at 150 °C. Crystalline thin films had cubic phase and rock salt structure. The average crystallite size of crystalline thin films was 22 nm, 28 nm and 29 nm for 150 °C, 200 °C and 250 °C respectively. From 150 °C to 250 °C increase in annealing temperature leads to increase in crystallite arrangement. FESEM images of thin films revealed that crystallite arrangement improved by increasing annealing temperature up to 250 °C. Increase in DC electrical conductivity by increasing temperature confirmed the semiconductor nature of crystalline thin films. Increase in dark current by increasing annealing temperature showed the effect of crystallite arrangement on carrier transport. Photosensitivity decreased by increasing annealing temperature for crystalline thin films that it was explained at the base of thermal quenching of photoconductivity and adsorption of oxygen at the surface of thin films that leads to the formation of PbO at higher temperatures.     

Epitaxial growth of Ge thin film on Si (001) by DC magnetron sputtering

We have demonstrated that sub-10 nm-thick heteroepitaxial Ge films on Si (001) having smooth surfaces can be obtained by DC magnetron sputtering. Ge films grown at 350 °C preserve the smooth surfaces with a roughness root mean square (RMS) of 0.39 nm, whereas, the Ge films grown at 500 °C show significant roughness with an island-like morphology. In samples grown at 350 °C, it is confirmed that the Ge films are grown epitaxially by cross-section transmission electron microscopy (TEM) and X-ray diffraction (XRD) rocking curve measurements. Rapid thermal annealing (RTA) at 720 °C is effective in improving the crystalline quality and the degradation in the roughness is negligible. Raman spectra and an XRD reciprocal space map reveal that the epitaxial Ge grown at 350 °C show an in-plane compressive strain and that the strain continues to remain after a 720 °C RTA.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Perylrene-based n-type field-effect transistors prepared by the neutral cluster beam deposition method

We present the first application of the neutral cluster beam deposition (NCBD) method to prepare n-type organic thin-film transistors with a top-contact structure based on N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13). Systematic analysis was carried out to examine the effects of surface passivation and thermal post-treatment on the morphology and crystallinity of P13 active layers and device performance, together with operational stability as a function of time. The high room-temperature field-effect mobility of 0.58 cm²/Vs for the thermally post-treated devices was obtained under ambient conditions. The comparative study of the transport mechanisms responsible for conduction of the electron carriers over a temperature range of 10–300 K indicated that surface modification and thermal post-treatment decrease total trap density and activation energy for carrier transport by reducing structural disorder.     

Growth and characterization of indium oxide diodes prepared by reactive magnetron sputtering

The electrical properties of Cr/Pt/Au and Ni/Au ohmic contacts with unintentionally doped In₂O₃ (U-In₂O₃) film and zinc-doped In₂O₃ (In₂O₃:Zn) prepared by reactive magnetron sputtering deposition are described. The lowest specific contact resistance of Cr/Pt/Au and Ni/Au is 2.94 × 10⁻⁶ and 1.49 × 10⁻² Ω-cm², respectively, as determined by the transmission line model (TLM) after heat treatment at 300 °C by thermal annealing for 10 min in nitrogen ambient. The indium oxide diodes have an ideality factor of 1.1 and a soft breakdown voltage of 5 V. The reverse leakage current prior to breakdown is around 10⁻⁵ A.     

Hybrid dual gate ferroelectric memory for multilevel information storage

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm² V⁻¹ s⁻¹, large memory window of ∼18 V, and a low sub-threshold swing ∼−4 V dec⁻¹. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.     

Thermal conductivity of AlN thin films deposited by RF magnetron sputtering

Aluminum nitride (AlN) film, which is being investigated as a possible passivation layer in inkjet printheads, was deposited on a Si (1 0 0) substrate at 400 °C by radio frequency (RF) magnetron sputtering using an AlN ceramic target. Dependence on various reactive gas compositions (Ar, Ar:H₂, Ar:N₂) during sputtering was investigated to determine thermal conductivity. The crystallinity, grain size, and Al–N bonding changes by the gas compositions were examined and are discussed in relation to thermal conductivity. Using an Ar and 4% H₂, the deposited AlN films were crystalline with larger grains. Using a higher nitrogen concentration of 10%, a near amorphous phase, finer morphology, and an enhanced Al–N bonding ratio were achieved. A high thermal conductivity of 134 W/mk, which is nine times higher than that of the conventional Si₃N₄ passivation film, was obtained with a 10% N₂ reactive gas mixture. A high Al–N bonding ratio in AlN film is considered the most important factor for higher thermal conductivity.     

Power cycle reliability of Cu nanoparticle joints with mismatched coefficients of thermal expansion

The power cycle reliability of Cu nanoparticle joints between Al₂O₃ heater chips and different heat sinks (Cu-40 wt.%Mo, Al-45 wt.%SiC and pure Cu) was studied to explore the effect of varying the mismatch in the coefficient of thermal expansion (CTE) between the heater chip and the heat sink from 4.9 to 10.3 ppm/K. These joints were prepared under a hydrogen atmosphere by thermal treatment at 250, 300 and 350 °C using a pressure of 1 MPa, and all remained intact after 3000 cycles of 65/200 °C and 65/250 °C when the CTE mismatch was less than 7.3 ppm/K, despite vertical cracks forming in the sintered Cu. When the CTE mismatch was 10.3 ppm/K, the Cu nanoparticle joint created at 300 °C endured the power cycle tests, but the joint created at 250 °C broke by lateral cracks in the sintered Cu after 1000 cycles of 65/200 °C. The Cu nanoparticle joint created at 350 °C also broke by vertical cracks in the heater chip after 1000 cycles of 65/250 °C, suggesting that although sintered Cu can be strengthened to tolerate the stress by increasing the joint temperature, this eventually causes the weak and brittle chip to fracture through accumulated stress. The calculation results of stresses on the heater chip showed that the stress can be higher than the strength of Al₂O₃ when the CTE mismatch is 10.3 ppm/K and the Young's modulus of the sintered Cu is higher than 20 GPa, suggesting that the heater chip can be broken.     

Improved reliability of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with high density silicon nitride passivation

We have systematically studied the effects of Si_xN_1 − x passivation density on the reliability of AlGaN/GaN high electron mobility transistors. Upon stressing, devices degrade in two stages, fast-mode degradation and followed by slow-mode degradation. Both degradations can be explained as different stages of pit formation at the gate-edge. Fast-mode degradation is caused by pre-existing oxygen at the Si_xN_1 − x/AlGaN interface. It is not significantly affected by the Si_xN_1 − x density. On the other hand, slow-mode degradation is associated with Si_xN_1 − x degradation. Si_xN_1 − x degrades through electric-field induced oxidation in discrete locations along the gate-edges. The size of these degraded locations ranged from 100 to 300 nm from the gate edge. There are about 16 degraded locations per 100 μm gate-width. In each degraded location, low density nano-globes are formed within the Si_xN_1 − x. Because of the low density of the degraded locations, oxygen can diffuse through these areas and oxidize the AlGaN/GaN to form pits. This slow-mode degradation can be minimized by using high density (ρ = 2.48 g/cm³) Si₃₆N₆₄ as the passivation layer. For slow-mode degradation, the median time to failure of devices with high density passivation is found to increase up to 2× as compared to the low density (ρ = 2.25 g/cm³) Si₄₃N₅₇ passivation. A model based on Johnson-Mehl-Avrami theory is proposed to explain the kinetics of pit formation.     

A high Schottky barrier between Ni and S-passivated n-type Si(1 0 0) surface

By minimizing surface states with sulfur passivation, a record-high Schottky barrier is achieved with nickel on n-type Si(1 0 0) surface. Capacitance–voltage measurements yield a flat-band barrier height of 0.97 eV. Activation-energy and current–voltage measurements indicate ～0.2-eV lower barriers for the Ni/Si(1 0 0) junction. These results accompany a previously-reported record-high Schottky barrier of 1.1 eV between aluminum and S-passivated p-type Si(1 0 0) surface. The operation of these metal/Si(1 0 0) junctions changes from majority-carrier conduction, i.e., a Schottky junction, to minority-carrier conduction, i.e., a p–n junction, with the increase in barrier height from 0.97 eV to 1.1 eV. Temperature-dependent current–voltage measurements reveal that the Ni/S-passivated n-type Si(1 0 0) junction is stable up to 110 °C.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Fabrication of nano-sized resist patterns on flexible plastic film using thermal curing nano-imprint lithography

Due to polymer’s excellent flexibility, transparency, reliability and light weight, it is a good candidate material for substrate of devices including organic electronic devices, biomedical devices, and flexible displays (LCD and OLED). In order to build such devices on polymer, nano- to micron-sized patterning must be accomplished. Since polymer materials reacts with organic solvents or developer solutions which are inevitably used in photolithography and cannot bear high temperature (∼140 °C) process for photoresist baking, conventional photolithography cannot be used to polymer substrate. In this research, monomer based thermal curing imprinting lithography was used to make as small as 100 nm dense line and space patterns on flexible PET (polyethylene-terephthalate) film. Compared to hot embossing lithography, monomer based thermal curing imprint lithography uses monomer based imprint resin which consists of base monomer and thermal initiator. Since it is liquid phase at room temperature and polymerization can be initiated at 85 °C, which is much lower than glass temperature of polymer resin, the pattern transfer can be done at much lower temperature and pressure. Hence, patterns as small as 100 nm were successfully fabricated on flexible PET film substrate by monomer based thermal curing imprinting lithography at 85 °C and 5 atm without any noticeable degradation of PET substrate.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.