Bipolar transistor with graded band-gap base

We report the first compositionally graded base bipolar transistor. The device grown by MBE incorporates a wide gap Al0.35Ga0.65As emitter (n = 2 × 1016/cm3 and a 0.4 ?m thick p+ (= 2 × 1018/cm3)base graded from Al0.20Ga0.80As to GaAs. DC current gain of 35 with flat, nearly ideal, collector characteristics are observed. Incorporation of a graded gap base gives much faster base transit times due to the induced quasi-electric field for electrons, thus allowing a precious tradeoff against the base resistance.     

Bipolar transistor with self-aligned lateral profile

This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.     

Field-effect transistor self-electrooptic effect device: integrated photodiode, quantum well modulator and transistor

The authors propose and demonstrate the integration of a photodiode, a quantum-confined Stark-effect quantum-well optical modulator, and a metal-semiconductor field-effect transistor (MESFET) to make a field-effect transistor self-electrooptic effect device. This integration allows optical inputs and outputs on the surface of a GaAs-integrated circuit chip, compatible with standard MESFET processing. To provide an illustration of feasibility, the authors demonstrate signal amplification with a single MESFET.<>     

Optimal quantum well width and the effect of quantum well position on the performance of transistor lasers

Transistor laser (TL) model based on InGaP/GaAs/InGaAs/GaAs is analyzed and presented. It is realized that quantum well (QW) with width of 10 nm may be formed for low base threshold current density J th . The emission wavelength is found to be 1.05 μm, and the indium (In) composition is 0.25 for optimal QW width. It is identified that J th decreases with the movement of QW towards the base-emitter (B-E) interface. Small signal optical response is calculated, and the effect of QW position is studied. The bandwidth is enhanced due to the movement of the QW towards the emitter base junction.     

Bipolar transistor: Two-dimensional effects on current gain and base transit time

Two-dimensional effects in bipolar devices with small dimensions are calculated analytically if simplifying assumptions are made e.g. uniformly doped regions and zero recombination. In this paper we treat effects of the emitter sidewalls on the current gain and the base transit time.

The current flows through the base and emitter are calculated for rectangular as well as curved emitter-base junctions. Current gain and base transit time are analysed as local variables, i.e. functions that vary along the 2-D emitter-base junction. In this way it can be seen where and how several parameters influence the overall performance of the device.

The total current gain is modified by the sidewalls; it increases if the distance between the emitter-base junction and the emitter metallisation is increased. However, this distance cannot be increased indefinitely because of finite recombination lifetimes.

The diffusion capacitance is strongly affected by the sidewalls. Because the sidewalls carry a considerable part of the current the transit time is less affected. However, the influence of the sidewalls is still noticeable. It is expected that in a transistor with a 1 μm wide and 0.15 μm deep emitter the transition frequency is already negatively influenced by the emitter sidewalls.     

Self-aligned transistor with sidewall base electrode

A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSI's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 14 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI.     

Complementary MOS—Bipolar transistor structure

Bipolar transistors can be used to increase the driving capabilities of complementary MOS transistors while retaining the low power dissipation feature. The fabrication of n-p-n bipolar transistors is compatible with the fabrication of the complementary MOS transistors in a monolithic structure. Common collector n-p-n transistors can be fabricated using a diffused n⁺source-drain region as emitter, a diffused p^-isolation region as base and an n^-substrate as collector with a hfegreater than 100. Lateral n-p-n transistors can be fabricated using a diffused n⁺source-drain region as emitter and collector, and p^-isolation region as base with a hfegreater than 10.     

Programmable memory cell using quantum confined Stark effect in multi-quantum well heterojunction bipolar transistor

A three terminal bistable programmable memory cell which can be read either optically or electrically is proposed and demonstrated. The device is based on using Stark effect of the excitonic transitions in a multi-quantum well base region of a heterojunction bipolar transistor. The single device can be flipped (and held) from low transmittance (high voltage) to high transmittance (low voltage) state and vice versa by a varying base current signal.<>     

Planar heterojunction bipolar transistor with an implanted base

A novel process to fabricate a planar emitter-up AlGaAs-GaAs heterojunction bipolar transistor HBT, has been developed relying on selective base implantation through the emitter and the heterojunction. The selective base definition means that all three transistor contacts can be made from the top surface, thereby making device integration easier because of the planar surface topology. This simple transistor fabrication process was examined using MOCVD material. Transistors with a DC current gain of 120 have been measured.<>     

An induced base hot-electron transistor

A novel three-terminal device is proposed in which the base represents an undoped quantum well in a graded-gap heterostructure. The base conductivity is provided by a two-dimensional electron gas induced by the collector field. The intrinsic delay time is estimated to be about 1 ps at room temperature with a common-base current gain close to unity.     

New field-effect transistor with quantum wire and modulation-dopedheterostructures

A new field-effect transistor, consisting of an AlGaAs/GaAs heterostructure and an (AlAs)_0.25(GaAs)_0.75 vertical superlattice, is fabricated. It has a large transconductance of 14 mS/mm at a gate length of 250 μm, corresponding to a transconductance of 3.5 S/mm for 1 μm gate length. Hall measurement revealed a novel FET operation mode called `velocity modulation'     

Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory     

Bipolar transistor design for optimized power-delay logic circuits

This design optimization scheme provides a procedure for tailoring the impurity doping profile of the transistor so that the performance of the logic circuit can be optimized at a specific power dissipation level and a given lithographic line width. It is shown that the condition of the optimized circuit performance dictates a set of relationships between the transistor structure, the logic voltage swing, and the value of the circuit elements. This paper further discusses the relation between the circuit properties and the transistor size, which becomes smaller as the lithography advances. It is concluded that as the horizontal dimensions are reduced, the vertical dimension of the transistor must be reduced, the impurity density increased, and the current density increased in order to increase the circuit speed. A simple relationship between the lithographic line width and the vertical structure is given which enables one to predict the power-speed performance for the reduced structure.     

Bipolar transistor epilayer design using the MAIDS mixed-levelsimulator

In this paper, we address the epilayer design of the bipolar transistor using the one-dimensional (1-D) mixed-level simulator MAIDS (microwave active integral device simulator). MAIDS facilitates simulation of the electrical behavior of bipolar (hetero) junction transistors with various doping profiles and under different signal conditions in a realistic circuit environment. MAIDS as implemented within Hewlett Packard's microwave design system is a useful and promising tool in the development of bipolar transistors for large-signal conditions. Using MAIDS, we have identified the dominant bipolar transistor distortion sources with respect to the biasing conditions. Simulation results are compared with small- and large-signal measurements for the BFQ135 transistor, which has been developed for cable television (CATV) applications. By analyzing the measured and simulated data, we have developed an optimum epilayer design map for third-order intermodulation distortion that has proven to be particularly useful in the epilayer dimensioning of transistors for CATV applications     

SiGe drift base bipolar transistor with self-aligned selectiveCVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 Ω (emitter area: 0.2×3 μm²), and an f_MAX of 37.1 GHz is achieved by employing 0.2-μm EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps     

Interferometric quantum well modulators with gain

Details on the design, fabrication and properties of the first interferometric intensity modulators with monolithically integrated optical gain are presented. These guided-wave devices make use of two sets of InP-based quantum well heterostructures that are contained in a single base wafer and individually designed for enhanced electrorefraction and amplification at 1.55 μm. The unique quantum well electrooptic properties as well as the fabrication techniques and waveguide design issues that determine final device performance are discussed     

A silicon quantum wire transistor with one-dimensional subband effects

A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology, electron beam lithography, anisotropic dry etching, and thermal oxidation. We have obtained the quantum wire with a width of 65 nm, which is fully embedded in silicon dioxide. This narrow dimension of the wire and large potential barrier between silicon and silicon dioxide make the electrons moving through the wire experience one-dimensional confinement. The step-like structure in the conductance versus gate voltage curve, which is a typical evidence of one-dimensional conductance, has been observed at temperatures below 4.2 K. A period of step appearance and a step size have been analyzed to compare experimental characteristics with theoretical calculation.     

Negative transconductance superlattice base bipolar transistor

The operation of a new superlattice base bipolar transistor is reported. Negative transconductance in the common-base transfer characteristic is achieved at an emitter-base voltage in excellent agreement with the bias required to suppress tunnel injection into the first miniband. In the common emitter configuration a corresponding peak in the current gain of the device is obtained as the base current is increased.<>